mirror of https://github.com/YosysHQ/yosys.git
Bugfix in fsm_map for FSMs without reset state
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@ -272,7 +272,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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}
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}
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else
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else
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{
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{
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RTLIL::SigSpec sig_a, sig_b, sig_s;
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RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width);
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RTLIL::SigSpec sig_b, sig_s;
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int reset_state = fsm_data.reset_state;
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int reset_state = fsm_data.reset_state;
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if (reset_state < 0)
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if (reset_state < 0)
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reset_state = 0;
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reset_state = 0;
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