mirror of https://github.com/YosysHQ/yosys.git
synth_xilinx to map_cells before map_luts
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ef84b434a5
commit
d9cb787391
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@ -113,17 +113,17 @@ struct SynthXilinxPass : public Pass
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
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log(" opt -fast\n");
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log(" opt -fast\n");
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log("\n");
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log("\n");
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log(" map_luts:\n");
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log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
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log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
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log(" clean\n");
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log("\n");
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log(" map_cells:\n");
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log(" map_cells:\n");
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log(" techmap -map +/xilinx/cells_map.v\n");
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log(" techmap -map +/xilinx/cells_map.v\n");
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log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
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log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
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log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
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log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
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log(" clean\n");
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log(" clean\n");
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log("\n");
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log("\n");
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log(" map_luts:\n");
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log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
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log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
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log(" clean\n");
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log("\n");
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log(" check:\n");
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log(" check:\n");
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log(" hierarchy -check\n");
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log(" hierarchy -check\n");
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log(" stat\n");
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log(" stat\n");
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@ -265,13 +265,6 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "opt -fast");
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Pass::call(design, "opt -fast");
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}
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}
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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Pass::call(design, "clean");
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Pass::call(design, "techmap -map +/xilinx/lut_map.v");
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}
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if (check_label(active, run_from, run_to, "map_cells"))
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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{
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Pass::call(design, "techmap -map +/xilinx/cells_map.v");
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Pass::call(design, "techmap -map +/xilinx/cells_map.v");
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@ -280,6 +273,13 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "clean");
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Pass::call(design, "clean");
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}
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}
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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Pass::call(design, "clean");
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Pass::call(design, "techmap -map +/xilinx/lut_map.v");
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}
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if (check_label(active, run_from, run_to, "check"))
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if (check_label(active, run_from, run_to, "check"))
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{
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{
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Pass::call(design, "hierarchy -check");
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Pass::call(design, "hierarchy -check");
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