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Move clean from aigerparse to abc9

This commit is contained in:
Eddie Hung 2019-04-23 13:42:35 -07:00
parent 91c3afcab7
commit d9c915042a
2 changed files with 1 additions and 2 deletions
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2
frontends/aiger/aigerparse.cc
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@ -598,8 +598,6 @@ next_line:
module->fixup_ports(); module->fixup_ports();
design->add(module); design->add(module);
Pass::call(design, "clean");
for (auto cell : module->cells().to_vector()) { for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue; if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit(); auto y_port = cell->getPort("\\Y").as_bit();

1
passes/techmap/abc9.cc
View File

@ -548,6 +548,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
if (mapped_mod == NULL) if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n"); log_error("ABC output file does not contain a module `netlist'.\n");
Pass::call(mapped_design, "clean");
pool<RTLIL::SigBit> output_bits; pool<RTLIL::SigBit> output_bits;
for (auto &it : mapped_mod->wires_) { for (auto &it : mapped_mod->wires_) {