Use new pmux2shiftx from #944, remove my old attempt

passes/techmap/Makefile.inc

@@ -37,7 +37,6 @@ OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
 OBJS += passes/techmap/dff2dffs.o
 OBJS += passes/techmap/flowmap.o
-OBJS += passes/techmap/pmux2shiftx.o
 endif
 
 GENFILES += passes/techmap/techmap.inc

passes/techmap/pmux2shiftx.cc

@@ -1,81 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct Pmux2ShiftxPass : public Pass {
-	Pmux2ShiftxPass() : Pass("pmux2shiftx", "transform $pmux cells to $shiftx cells") { }
-	void help() YS_OVERRIDE
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    pmux2shiftx [selection]\n");
-		log("\n");
-		log("This pass transforms $pmux cells to $shiftx cells.\n");
-		log("\n");
-	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing PMUX2SHIFTX pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
-
-		for (auto module : design->selected_modules())
-		for (auto cell : module->selected_cells())
-		{
-			if (cell->type != "$pmux")
-				continue;
-
-			// Create a new encoder, out of a $pmux, that takes
-			// the existing pmux's 'S' input and transforms it
-			// back into a binary value
-			RTLIL::SigSpec shiftx_a;
-			RTLIL::SigSpec pmux_s;
-
-			int s_width = cell->getParam("\\S_WIDTH").as_int();
-			if (!cell->getPort("\\A").is_fully_undef()) {
-				++s_width;
-				shiftx_a.append(cell->getPort("\\A"));
-				pmux_s.append(module->Not(NEW_ID, module->ReduceOr(NEW_ID, cell->getPort("\\S"))));
-			}
-			const int clog2width = ceil(log2(s_width));
-
-			RTLIL::SigSpec pmux_b;
-			for (int i = s_width-1; i >= 0; i--)
-				pmux_b.append(RTLIL::Const(i, clog2width));
-			shiftx_a.append(cell->getPort("\\B"));
-			pmux_s.append(cell->getPort("\\S"));
-
-			RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width);
-			module->addPmux(NEW_ID, RTLIL::Const(RTLIL::Sx, clog2width), pmux_b, pmux_s, pmux_y);
-			module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y"));
-			module->remove(cell);
-		}
-	}
-} Pmux2ShiftxPass;
-
-PRIVATE_NAMESPACE_END

passes/techmap/shregmap.cc

@@ -96,7 +96,6 @@ struct ShregmapTechGreenpak4 : ShregmapTech
 struct ShregmapTechXilinx7 : ShregmapTech
 {
 	dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
-	dict<SigBit, SigSpec> sigbit_to_eq_input;
 	const ShregmapOptions &opts;
 
 	ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
@@ -120,32 +119,6 @@ struct ShregmapTechXilinx7 : ShregmapTech
 				for (auto bit : sigmap(cell->getPort("\\B")))
 					sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
 			}
-			else if (cell->type == "$pmux") {
-				if (!cell->get_bool_attribute("\\shiftx_compatible")) continue;
-				int width = cell->getParam("\\WIDTH").as_int();
-				int j = 0;
-				for (auto bit : sigmap(cell->getPort("\\A")))
-					sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
-				j = cell->getParam("\\S_WIDTH").as_int();
-				int k = 0;
-				for (auto bit : sigmap(cell->getPort("\\B"))) {
-					sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j, k++);
-					if (k == width) {
-						k = 0;
-						--j;
-					}
-				}
-				log_assert(j == 0);
-			}
-			else if (cell->type == "$eq") {
-				auto b_wire = cell->getPort("\\B");
-				// Keep track of $eq cells that compare against the value 1
-				// in anticipation that they drive the select (S) port of a $pmux
-				if (b_wire.is_fully_const() && b_wire.as_int() == 1) {
-					auto y_wire = sigmap(cell->getPort("\\Y").as_bit());
-					sigbit_to_eq_input[y_wire] = cell->getPort("\\A");
-				}
-			}
 		}
 	}
 
@@ -157,8 +130,6 @@ struct ShregmapTechXilinx7 : ShregmapTech
 		if (cell) {
 			if (cell->type == "$shiftx" && port == "\\A")
 				return;
-			if (cell->type == "$pmux" && (port == "\\A" || port == "\\B"))
-				return;
 			if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
 				return;
 		}
@@ -210,10 +181,6 @@ struct ShregmapTechXilinx7 : ShregmapTech
 			if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
 				return false;
 		}
-		else if (shiftx->type == "$pmux") {
-			if (GetSize(taps) != shiftx->getParam("\\S_WIDTH").as_int() + 1)
-				return false;
-		}
 		else if (shiftx->type == "$mux") {
 			if (GetSize(taps) != 2)
 				return false;
@@ -250,25 +217,6 @@ struct ShregmapTechXilinx7 : ShregmapTech
 			q_wire = shiftx->getPort("\\Y");
 			shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
 		}
-		else if (shiftx->type == "$pmux") {
-			// If the 'A' port is fully undef, then opt_expr -mux_undef
-			// has not been applied, so find the second-to-last bit of
-			// the 'S' port (corresponding to $eq cell comparing for 1)
-			// otherwise use the last bit of 'S'
-			const auto& s_wire_bits = shiftx->getPort("\\S").bits();
-			SigBit s1;
-			if (shiftx->getPort("\\A").is_fully_undef())
-				s1 = s_wire_bits[s_wire_bits.size() - 2];
-			else
-				s1 = s_wire_bits[s_wire_bits.size() - 1];
-			RTLIL::SigSpec y_wire = shiftx->getPort("\\Y");
-			l_wire = sigbit_to_eq_input.at(s1);
-			log_assert(l_wire.size() == ceil(log2(taps.size())));
-			int group = std::get<2>(it->second);
-			q_wire = y_wire[group];
-			y_wire[group] = cell->module->addWire(NEW_ID);
-			shiftx->setPort("\\Y", y_wire);
-		}
 		else if (shiftx->type == "$mux") {
 			l_wire = shiftx->getPort("\\S");
 			q_wire = shiftx->getPort("\\Y");

techlibs/xilinx/synth_xilinx.cc

@@ -112,9 +112,11 @@ struct SynthXilinxPass : public Pass
 		log("        memory_map\n");
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
-		log("        opt -full\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
+		log("        pmux2shiftx (without '-nosrl' only)\n");
+		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
+		log("        opt -full\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
 		log("        opt -fast\n");
 		log("\n");
@@ -261,17 +263,20 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "fine"))
 		{
-			Pass::call(design, "opt -fast -full");
+			Pass::call(design, "opt -fast");
 			Pass::call(design, "memory_map");
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
-			Pass::call(design, "opt -full");
 
 			if (!nosrl) {
 				Pass::call(design, "simplemap t:$dff t:$dffe");
+				Pass::call(design, "pmux2shiftx");
+				Pass::call(design, "opt_expr -mux_undef");
 				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 			}
 
+			Pass::call(design, "opt -full");
+
 			if (vpr) {
 				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
 			} else {