From 53cf38c65680f3c254a55bda81b6ced19db01b14 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Wed, 18 Dec 2024 11:36:21 -0800 Subject: [PATCH] Leave comment about signage assumption --- passes/pmgen/peepopt_muldiv_c.pmg | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/pmgen/peepopt_muldiv_c.pmg b/passes/pmgen/peepopt_muldiv_c.pmg index c2d7add17..78b5e768a 100644 --- a/passes/pmgen/peepopt_muldiv_c.pmg +++ b/passes/pmgen/peepopt_muldiv_c.pmg @@ -48,6 +48,7 @@ code // Get properties and values of b_const and c_const int b_const_width = mul->getParam(ID::B_WIDTH).as_int(); + // b_const may be coming from the A port but it's an RTLIL invariant that A_SIGNED equals B_SIGNED bool b_const_signed = mul->getParam(ID::B_SIGNED).as_bool(); bool c_const_signed = div->getParam(ID::B_SIGNED).as_bool(); int b_const_int = b_const.as_int(b_const_signed);