riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Tabs to spaces in opt_share examples

This commit is contained in:
Bogdan Vukobratovic 2019-08-03 12:35:46 +02:00
parent 280c4e7794
commit d8be5ce6ba
10 changed files with 150 additions and 150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
tests/opt/opt_share_add_sub.v
View File

@ -1,10 +1,10 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input sel, input sel,
output [15:0] res, output [15:0] res,
); );
assign res = {sel ? a + b : a - b}; assign res = {sel ? a + b : a - b};
endmodule endmodule

20
tests/opt/opt_share_cat.v
View File

@ -1,15 +1,15 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input sel, input sel,
output [63:0] res, output [63:0] res,
); );
reg [31: 0] cat1 = {a+b, c+d}; reg [31: 0] cat1 = {a+b, c+d};
reg [31: 0] cat2 = {a-b, c-d}; reg [31: 0] cat2 = {a-b, c-d};
assign res = {b, sel ? cat1 : cat2, a}; assign res = {b, sel ? cat1 : cat2, a};
endmodule endmodule

34
tests/opt/opt_share_cat_multiuser.v
View File

@ -1,22 +1,22 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input sel, input sel,
output reg [47:0] res, output reg [47:0] res,
); );
wire [15:0] add_res = a+b; wire [15:0] add_res = a+b;
wire [15:0] sub_res = a-b; wire [15:0] sub_res = a-b;
wire [31: 0] cat1 = {add_res, c+d}; wire [31: 0] cat1 = {add_res, c+d};
wire [31: 0] cat2 = {sub_res, c-d}; wire [31: 0] cat2 = {sub_res, c-d};
always @* begin always @* begin
case(sel) case(sel)
0: res = {cat1, add_res}; 0: res = {cat1, add_res};
1: res = {cat2, add_res}; 1: res = {cat2, add_res};
endcase endcase
end end
endmodule endmodule

32
tests/opt/opt_share_diff_port_widths.v
View File

@ -1,21 +1,21 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [1:0] sel, input [1:0] sel,
output reg [15:0] res output reg [15:0] res
); );
wire [15:0] add0_res = a+b; wire [15:0] add0_res = a+b;
wire [15:0] add1_res = a+c; wire [15:0] add1_res = a+c;
always @* begin always @* begin
case(sel) case(sel)
0: res = add0_res[10:0]; 0: res = add0_res[10:0];
1: res = add1_res[10:0]; 1: res = add1_res[10:0];
2: res = a - b; 2: res = a - b;
default: res = 32'bx; default: res = 32'bx;
endcase endcase
end end
endmodule endmodule

28
tests/opt/opt_share_extend.v
View File

@ -1,18 +1,18 @@
module opt_share_test( module opt_share_test(
input signed [7:0] a, input signed [7:0] a,
input signed [10:0] b, input signed [10:0] b,
input signed [15:0] c, input signed [15:0] c,
input [1:0] sel, input [1:0] sel,
output reg signed [15:0] res output reg signed [15:0] res
); );
always @* begin always @* begin
case(sel) case(sel)
0: res = a + b; 0: res = a + b;
1: res = a - b; 1: res = a - b;
2: res = a + c; 2: res = a + c;
default: res = 16'bx; default: res = 16'bx;
endcase endcase
end end
endmodule endmodule

34
tests/opt/opt_share_large_pmux_cat.v
View File

@ -1,21 +1,21 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [2:0] sel, input [2:0] sel,
output reg [31:0] res output reg [31:0] res
); );
always @* begin always @* begin
case(sel) case(sel)
0: res = {a + b, a}; 0: res = {a + b, a};
1: res = {a - b, b}; 1: res = {a - b, b};
2: res = {a + c, c}; 2: res = {a + c, c};
3: res = {a - c, a}; 3: res = {a - c, a};
4: res = {b, b}; 4: res = {b, b};
5: res = {c, c}; 5: res = {c, c};
default: res = 32'bx; default: res = 32'bx;
endcase endcase
end end
endmodule endmodule

40
tests/opt/opt_share_large_pmux_cat_multipart.v
View File

@ -1,25 +1,25 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input [2:0] sel, input [2:0] sel,
output reg [31:0] res output reg [31:0] res
); );
wire [15:0] add0_res = a+d; wire [15:0] add0_res = a+d;
always @* begin always @* begin
case(sel) case(sel)
0: res = {add0_res, a}; 0: res = {add0_res, a};
1: res = {a - b, add0_res[7], 15'b0}; 1: res = {a - b, add0_res[7], 15'b0};
2: res = {b-a, b}; 2: res = {b-a, b};
3: res = {d, b - c}; 3: res = {d, b - c};
4: res = {d, b - a}; 4: res = {d, b - a};
5: res = {c, d}; 5: res = {c, d};
6: res = {a - c, b-d}; 6: res = {a - c, b-d};
default: res = 32'bx; default: res = 32'bx;
endcase endcase
end end
endmodule endmodule

38
tests/opt/opt_share_large_pmux_multipart.v
View File

@ -1,23 +1,23 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input [2:0] sel, input [2:0] sel,
output reg [15:0] res output reg [15:0] res
); );
always @* begin always @* begin
case(sel) case(sel)
0: res = a + d; 0: res = a + d;
1: res = a - b; 1: res = a - b;
2: res = b; 2: res = b;
3: res = b - c; 3: res = b - c;
4: res = b - a; 4: res = b - a;
5: res = c; 5: res = c;
6: res = a - c; 6: res = a - c;
default: res = 16'bx; default: res = 16'bx;
endcase endcase
end end
endmodule endmodule

34
tests/opt/opt_share_large_pmux_part.v
View File

@ -1,21 +1,21 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [2:0] sel, input [2:0] sel,
output reg [15:0] res output reg [15:0] res
); );
always @* begin always @* begin
case(sel) case(sel)
0: res = a + b; 0: res = a + b;
1: res = a - b; 1: res = a - b;
2: res = a + c; 2: res = a + c;
3: res = a - c; 3: res = a - c;
4: res = b; 4: res = b;
5: res = c; 5: res = c;
default: res = 16'bx; default: res = 16'bx;
endcase endcase
end end
endmodule endmodule

28
tests/opt/opt_share_mux_tree.v
View File

@ -1,18 +1,18 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [1:0] sel, input [1:0] sel,
output reg [15:0] res output reg [15:0] res
); );
always @* begin always @* begin
case(sel) case(sel)
0: res = a + b; 0: res = a + b;
1: res = a - b; 1: res = a - b;
2: res = a + c; 2: res = a + c;
default: res = 16'bx; default: res = 16'bx;
endcase endcase
end end
endmodule endmodule