Convert todo comments to directives

Could be left in for final version, but my current thinking is not?

docs/source/conf.py

@@ -59,6 +59,10 @@ latex_elements = {
 '''
 }
 
+# include todos during rewrite
+extensions.append('sphinx.ext.todo')
+todo_include_todos = True
+
 def setup(sphinx):
 	sys.path += [os.path.dirname(__file__) + "/../util"]
 	from RtlilLexer import RtlilLexer

docs/source/getting_started/scripting_intro.rst

@@ -1,7 +1,7 @@
 Scripting in Yosys
 ------------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Yosys reads and processes commands from synthesis scripts, command line
 arguments and an interactive command prompt. Yosys commands consist of a command

docs/source/getting_started/typical_phases.rst

@@ -1,7 +1,7 @@
 Typical phases of a synthesis flow
 ----------------------------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 - Reading and elaborating the design
 - Higher-level synthesis and optimization

docs/source/index.rst

@@ -12,3 +12,8 @@ Yosys Open SYnthesis Suite
 	test_suites
 
 	appendix
+
+TODOs
+-----
+
+.. todolist::

docs/source/introduction.rst

@@ -1,7 +1,7 @@
 What is Yosys
 =============
 
-.. TODO: rewrite to not be a thesis abstract
+.. todo:: rewrite to not be a thesis abstract
 
 :Abstract:
 	Most of today's digital design is done in HDL code (mostly Verilog or 
@@ -125,7 +125,7 @@ In no particular order:
 History of Yosys
 ----------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 A Hardware Description Language (HDL) is a computer language used to describe
 circuits. A HDL synthesis tool is a computer program that takes a formal

docs/source/test_suites.rst

@@ -4,7 +4,7 @@ Test suites
 .. note:: Potentially significantly out of date information
     last updated circa 2015
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Continuously checking the correctness of Yosys and making sure that new features
 do not break old ones is a high priority in Yosys.  Two external test suites

docs/source/using_yosys/more_scripting/opt_passes.rst

@@ -3,7 +3,7 @@
 Optimization passes
 ===================
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Yosys employs a number of optimizations to generate better and cleaner results.
 This chapter outlines these optimizations.

docs/source/using_yosys/more_scripting/selections.rst

@@ -1,8 +1,7 @@
 Selections
 ----------
 
-.. TODO: copypaste
-
+.. todo:: copypaste
 
 Most Yosys commands make use of the "selection framework" of Yosys. It can be
 used to apply commands only to part of the design. For example:

docs/source/yosys_internals/extensions.rst

@@ -3,7 +3,7 @@
 Writing extensions
 ==================
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 This chapter contains some bits and pieces of information about programming
 yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
@@ -81,7 +81,7 @@ look at the output of ``dump`` and ``show`` before and after the command has
 been executed can be helpful.  The :doc:`/using_yosys/more_scripting/selections`
 document has more information on using these commands.
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Creating modules from scratch
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

docs/source/yosys_internals/flow/command_ordering.rst

@@ -1,7 +1,7 @@
 Command ordering
 ----------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Intro to coarse-grain synthesis
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -36,7 +36,7 @@ The extract pass
   with an instance of the module from the map file.
 - In a way the ``extract`` pass is the inverse of the techmap pass.
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. figure:: ../../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
     :class: width-helper
@@ -118,7 +118,7 @@ Preconditioning: ``macc_xilinx_swap_map.v``
 
 Make sure ``A`` is the smaller port on all multipliers
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. literalinclude:: ../../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
    :language: verilog

docs/source/yosys_internals/flow/control_and_data.rst

@@ -1,7 +1,7 @@
 Control and data flow
 =====================
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 The data- and control-flow of a typical synthesis tool is very similar to the
 data- and control-flow of a typical compiler: different subsystems are called in

docs/source/yosys_internals/flow/model_checking.rst

@@ -1,7 +1,7 @@
 Symbolic model checking
 -----------------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. note:: 
     

docs/source/yosys_internals/flow/overview.rst

@@ -1,7 +1,7 @@
 Flow overview
 =============
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 :numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
 Yosys. Rectangles in the figure represent program modules and ellipses internal

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -639,13 +639,15 @@ to extend the actual Verilog frontend.
 Synthesizing Verilog arrays
 ---------------------------
 
-.. TODO: these
+.. todo:: 
 
-Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
-how they are processed in the memory pass.
+  Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
+  how they are processed in the memory pass.
 
 Synthesizing parametric designs
 -------------------------------
 
-Add some information on the ``RTLIL::Module::derive()`` method and how it is
-used to synthesize parametric modules via the hierarchy pass.
+.. todo::
+
+  Add some information on the ``RTLIL::Module::derive()`` method and how it is
+  used to synthesize parametric modules via the hierarchy pass.

docs/source/yosys_internals/formats/cell_library.rst

@@ -1,7 +1,7 @@
 .. role:: verilog(code)
 	:language: Verilog
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. _chapter:celllib:
 

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -74,7 +74,7 @@ This has three advantages:
 -  First, it is impossible that an auto-generated identifier collides with an
    identifier that was provided by the user.
 
-.. TODO: does opt_rmunused (still?) exist?
+.. todo:: does opt_rmunused (still?) exist?
 
 -  Second, the information about which identifiers were originally provided by
    the user is always available which can help guide some optimizations. For

docs/source/yosys_internals/index.rst

@@ -3,7 +3,7 @@
 Yosys internals
 ===============
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Yosys is an extensible open source hardware synthesis tool. It is aimed at
 designers who are looking for an easily accessible, universal, and
@@ -38,4 +38,4 @@ can be used as reference to implement a similar system in any language.
 	techmap
 	extensions
 
-.. TODO: copypaste
+.. todo:: copypaste

docs/source/yosys_internals/techmap.rst

@@ -1,6 +1,6 @@
 .. _chapter:techmap:
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Technology mapping 
 ==================
@@ -109,7 +109,7 @@ sensitive information from the Liberty file.
 Techmap by example
 ------------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 As a quick recap, the ``techmap`` command replaces cells in the design with
 implementations given as Verilog code (called "map files"). It can replace