mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3087 from tgingold-cern/sf2
complete support for microsemi smartfusion2 and igloo2bar
This commit is contained in:
Miodrag Milanović
GitHub
commit
d8a383b555
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@ -0,0 +1,84 @@
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Using yosys with Libero Soc
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===========================
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Yosys does synthesis and therefore could be used instead of Synplify in
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the Libero workflow. You still have to use LiberoSoc for place, route,
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bitsteam generation, timing analysis...
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This is unfortunately not trivial, but this is also not too difficult.
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When you run the Synthesize step, three tools are executed one after the other.
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You'd better to write a simple script, like this one (assuming the top module
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is top):
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----------- run_yosys.sh --------------
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#!/bin/sh
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set -e
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yosys -p 'read_verilog hdl/top.v; synth_sf2; write_verilog -defparam synthesis/top_yosys.v'
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rwnetlist64 --script yosys/rwnetlist.tcl
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echo "##### run g4compile"
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g4compile --script yosys/run_compile.tcl
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libero SCRIPT:run_yosys.tcl
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------------------------------------
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Yosys will do the synthesis and write a netlist in verilog. Then you have
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to call microsemi tools to build the netlist for the P&R tools.
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The first one do a file format conversion. During the normal workflow, the
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tcl file is created in a temporary file. You can use this one:
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------------- tcl/rwnetlist.tcl ---------
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set_device -fam SmartFusion2
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read_verilog \
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-file {../synthesis/top_yosys.v}
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write_adl -file {../designer/top/top.adl}
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----------------------------------------
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Probably, you will have to change the family for Igloo2.
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The second command link the netlists. The tcl script is generated by
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liberoSoc in designer/top/run_compile.tcl. You can use it as it.
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The "Source Files" value could be changed but it looks to have no effect.
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This commands create the .afl file.
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Then you can use the normal flow. This is done by the run_yosys.tcl:
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----------- run_yosys.tcl --------------
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open_project -file {./top.prjx}
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run_tool -name {PLACEROUTE}
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run_tool -name {PROGRAMDEVICE}
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-----------------------------------------
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Using MSS, HPMS or other IPs
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============================
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This works. You'd better to configure CCC (~ the PLL) and the MSS using
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liberoSoc as the configuration bits are not documented.
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Then you have to manually gather the HDL sources generated for the IPs.
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They are in the component subdirectory. Sometimes there are both a _syn and
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a _pre version of the same file. They are for symplify and precision.
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Use only once, the symplify version should be OK. For the MSS, these are the
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blackboxes, so you don't need them.
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SYSRESET and XTLOSC have one fake port. This is handled, provided you use
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the blackbox module declared by Yosys in cell_sim.v. This is OK by default
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too.
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What is missing
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===============
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Always flatten your design (this is the default). Hierarchical designs
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don't work.
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Constraints (SDC files) are not supported by Yosys. Furthermore, due to
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flattening and optimization, nets name may change.
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More testing...
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@ -17,5 +17,53 @@
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*
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*/
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(* techmap_celltype = "$alu" *)
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module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA, BB;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO, CI};
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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ARI1 #(
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// G = F1 = A[i] & (B[i]^BI)
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// Y = F0 = A[i]^B[i]^BI
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// P = Y
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// ADCB
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.INIT(20'b 01_11_0010_1000_1001_0110)
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) carry (
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.A(1'b0),
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.B(AA[i]),
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.C(BB[i]),
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.D(BI),
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.FCI(C[i]),
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.Y(X[i]),
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.S(Y[i]),
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.FCO(CO[i])
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);
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end endgenerate
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endmodule
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// nothing here yet
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@ -152,12 +152,26 @@ module SLE (
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assign Q = LAT ? q_latch : q_ff;
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endmodule
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// module AR1
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module ARI1 (
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input A, B, C, D, FCI,
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output Y, S, FCO
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);
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parameter [19:0] INIT = 20'h0;
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wire [2:0] Fsel = {D, C, B};
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wire F0 = INIT[Fsel];
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wire F1 = INIT[8 + Fsel];
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wire Yout = A ? F1 : F0;
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assign Y = Yout;
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wire S = FCI ^ Yout;
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wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
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wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
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assign FCO = P ? FCI : G;
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endmodule
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// module FCEND_BUFF
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// module FCINIT_BUFF
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// module FLASH_FREEZE
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// module OSCILLATOR
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// module SYSRESET
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// module SYSCTRL_RESET_STATUS
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// module LIVE_PROBE_FB
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@ -333,6 +347,7 @@ module BIBUF (
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inout PAD,
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output Y
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);
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parameter IOSTD = "";
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assign PAD = E ? D : 1'bz;
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assign Y = PAD;
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endmodule
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@ -347,6 +362,7 @@ module BIBUF_DIFF (
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inout PADN,
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output Y
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);
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parameter IOSTD = "";
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endmodule
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module CLKBIBUF (
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@ -357,6 +373,7 @@ module CLKBIBUF (
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(* clkbuf_driver *)
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output Y
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);
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parameter IOSTD = "";
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assign PAD = E ? D : 1'bz;
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assign Y = PAD;
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endmodule
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@ -367,6 +384,7 @@ module CLKBUF (
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(* clkbuf_driver *)
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output Y
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);
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parameter IOSTD = "";
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assign Y = PAD;
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endmodule
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@ -379,6 +397,7 @@ module CLKBUF_DIFF (
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(* clkbuf_driver *)
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output Y
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);
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parameter IOSTD = "";
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endmodule
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module INBUF (
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@ -386,6 +405,7 @@ module INBUF (
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input PAD,
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output Y
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);
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parameter IOSTD = "";
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assign Y = PAD;
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endmodule
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@ -397,6 +417,7 @@ module INBUF_DIFF (
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input PADN,
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output Y
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);
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parameter IOSTD = "";
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endmodule
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module OUTBUF (
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@ -404,6 +425,7 @@ module OUTBUF (
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(* iopad_external_pin *)
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output PAD
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);
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parameter IOSTD = "";
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assign PAD = D;
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endmodule
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@ -415,6 +437,7 @@ module OUTBUF_DIFF (
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(* iopad_external_pin *)
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output PADN
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);
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parameter IOSTD = "";
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endmodule
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module TRIBUFF (
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@ -423,6 +446,7 @@ module TRIBUFF (
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(* iopad_external_pin *)
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output PAD
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);
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parameter IOSTD = "";
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assign PAD = E ? D : 1'bz;
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endmodule
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@ -435,6 +459,7 @@ module TRIBUFF_DIFF (
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(* iopad_external_pin *)
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output PADN
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);
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parameter IOSTD = "";
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endmodule
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// module DDR_IN
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@ -442,3 +467,113 @@ endmodule
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// module RAM1K18
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// module RAM64x18
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// module MACC
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(* blackbox *)
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module SYSRESET (
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(* iopad_external_pin *)
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input DEVRST_N,
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output POWER_ON_RESET_N);
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endmodule
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(* blackbox *)
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module XTLOSC (
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(* iopad_external_pin *)
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input XTL,
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output CLKOUT);
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parameter [1:0] MODE = 2'h3;
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parameter real FREQUENCY = 20.0;
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endmodule
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(* blackbox *)
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module RAM1K18 (
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input [13:0] A_ADDR,
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input [2:0] A_BLK,
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(* clkbuf_sink *)
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input A_CLK,
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input [17:0] A_DIN,
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output [17:0] A_DOUT,
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input [1:0] A_WEN,
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input [2:0] A_WIDTH,
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input A_WMODE,
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input A_ARST_N,
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input A_DOUT_LAT,
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input A_DOUT_ARST_N,
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(* clkbuf_sink *)
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input A_DOUT_CLK,
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input A_DOUT_EN,
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input A_DOUT_SRST_N,
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input [13:0] B_ADDR,
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input [2:0] B_BLK,
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(* clkbuf_sink *)
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input B_CLK,
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input [17:0] B_DIN,
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output [17:0] B_DOUT,
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input [1:0] B_WEN,
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input [2:0] B_WIDTH,
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input B_WMODE,
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input B_ARST_N,
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input B_DOUT_LAT,
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input B_DOUT_ARST_N,
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(* clkbuf_sink *)
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input B_DOUT_CLK,
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input B_DOUT_EN,
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input B_DOUT_SRST_N,
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input A_EN,
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input B_EN,
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input SII_LOCK,
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output BUSY);
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endmodule
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(* blackbox *)
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module RAM64x18 (
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input [9:0] A_ADDR,
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input [1:0] A_BLK,
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input [2:0] A_WIDTH,
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output [17:0] A_DOUT,
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input A_DOUT_ARST_N,
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(* clkbuf_sink *)
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input A_DOUT_CLK,
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input A_DOUT_EN,
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input A_DOUT_LAT,
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input A_DOUT_SRST_N,
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(* clkbuf_sink *)
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input A_ADDR_CLK,
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input A_ADDR_EN,
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input A_ADDR_LAT,
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input A_ADDR_SRST_N,
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input A_ADDR_ARST_N,
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input [9:0] B_ADDR,
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input [1:0] B_BLK,
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input [2:0] B_WIDTH,
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output [17:0] B_DOUT,
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input B_DOUT_ARST_N,
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(* clkbuf_sink *)
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input B_DOUT_CLK,
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input B_DOUT_EN,
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input B_DOUT_LAT,
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input B_DOUT_SRST_N,
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(* clkbuf_sink *)
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input B_ADDR_CLK,
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input B_ADDR_EN,
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input B_ADDR_LAT,
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input B_ADDR_SRST_N,
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input B_ADDR_ARST_N,
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input [9:0] C_ADDR,
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(* clkbuf_sink *)
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input C_CLK,
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input [17:0] C_DIN,
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input C_WEN,
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input [1:0] C_BLK,
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input [2:0] C_WIDTH,
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input A_EN,
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input B_EN,
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input C_EN,
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input SII_LOCK,
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output BUSY);
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endmodule
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@ -66,6 +66,9 @@ struct SynthSf2Pass : public ScriptPass
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log(" -clkbuf\n");
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log(" insert direct PAD->global_net buffers\n");
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log("\n");
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log(" -discard-ffinit\n");
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log(" discard FF init value instead of emitting an error\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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@ -76,7 +79,7 @@ struct SynthSf2Pass : public ScriptPass
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}
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string top_opt, edif_file, vlog_file, json_file;
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bool flatten, retime, iobs, clkbuf;
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bool flatten, retime, iobs, clkbuf, discard_ffinit;
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void clear_flags() override
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{
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@ -88,6 +91,7 @@ struct SynthSf2Pass : public ScriptPass
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retime = false;
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iobs = true;
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clkbuf = false;
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discard_ffinit = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -138,6 +142,10 @@ struct SynthSf2Pass : public ScriptPass
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clkbuf = true;
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continue;
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}
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if (args[argidx] == "-discard-ffinit") {
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discard_ffinit = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -171,6 +179,8 @@ struct SynthSf2Pass : public ScriptPass
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if (check_label("coarse"))
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{
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if (discard_ffinit || help_mode)
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run("attrmap -remove init", "(only if -discard-ffinit)");
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run("synth -run coarse");
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}
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@ -218,9 +228,9 @@ struct SynthSf2Pass : public ScriptPass
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} else {
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run("clkbufmap -buf CLKINT Y:A");
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}
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run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs");
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run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs)");
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}
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run("clean");
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run("clean -purge");
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}
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if (check_label("check"))
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|
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@ -0,0 +1,22 @@
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# Our implementation
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read_verilog ../arith_map.v
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read_verilog ../cells_sim.v
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read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
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rename \$__SF2_ALU gate
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hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
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flatten
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opt
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write_verilog gate.v
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# The reference
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read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
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rename \$alu gold
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hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
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flatten
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proc
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clean
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write_verilog gold.v
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read_verilog gate.v
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miter -equiv -flatten -make_outputs gold gate miter
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sat -verify -prove trigger 0 -show-ports miter
|
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