mirror of https://github.com/YosysHQ/yosys.git
Include module name for area summary stats
The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~
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@ -142,7 +142,7 @@ struct statdata_t
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}
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}
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}
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}
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void log_data()
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void log_data(RTLIL::IdString mod_name, bool top_mod)
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{
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{
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log(" Number of wires: %6d\n", num_wires);
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log(" Number of wires: %6d\n", num_wires);
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log(" Number of wire bits: %6d\n", num_wire_bits);
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log(" Number of wire bits: %6d\n", num_wire_bits);
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@ -163,7 +163,7 @@ struct statdata_t
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if (area != 0) {
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if (area != 0) {
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log("\n");
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log("\n");
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log(" Chip area for this module: %f\n", area);
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log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
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}
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}
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}
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}
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};
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};
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@ -275,7 +275,7 @@ struct StatPass : public Pass {
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log("\n");
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log("\n");
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log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
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log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
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log("\n");
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log("\n");
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data.log_data();
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data.log_data(mod->name, false);
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}
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}
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if (top_mod != NULL && GetSize(mod_stat) > 1)
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if (top_mod != NULL && GetSize(mod_stat) > 1)
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@ -288,7 +288,7 @@ struct StatPass : public Pass {
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statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
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statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
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log("\n");
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log("\n");
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data.log_data();
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data.log_data(top_mod->name, true);
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}
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}
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log("\n");
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log("\n");
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