Merge remote-tracking branch 'origin/master' into xaig

passes/pmgen/README.md

@@ -83,8 +83,8 @@ They are declared like state variables, just using the `udata` statement:
     udata <int> min_data_width max_data_width
     udata <IdString> data_port_name
 
-They are atomatically initialzed to the default constructed value of their type
+They are automatically initialized to the default constructed value of their type
-when ther pattern matcher object is constructed.
+when the pattern matcher object is constructed.
 
 Embedded C++ code
 -----------------
@@ -158,7 +158,7 @@ Finally, `filter <expression>` narrows down the remaining list of cells. For
 performance reasons `filter` statements should only be used for things that
 can't be done using `select` and `index`.
 
-The `optional` statement marks optional matches. I.e. the matcher will also
+The `optional` statement marks optional matches. That is, the matcher will also
 explore the case where `mul` is set to `nullptr`. Without the `optional`
 statement a match may only be assigned nullptr when one of the `if` expressions
 evaluates to `false`.

passes/proc/proc_rmdead.cc

@@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
 
 	for (size_t i = 0; i < sw->cases.size(); i++)
 	{
-		bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0);
+		bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0;
 
 		for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
 			RTLIL::SigSpec sig = sw->cases[i]->compare[j];

techlibs/intel/cyclonev/cells_sim.v

@@ -85,7 +85,7 @@ module cyclonev_lcell_comb
       begin
          upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
          lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
-         lut5            = (datae) ? upper_mask_value : lower_mask_value;
+         lut5            = (datae) ? upper_lut_value : lower_lut_value;
       end
    endfunction // lut5
 
@@ -95,15 +95,16 @@ module cyclonev_lcell_comb
       input        dataa, datab, datac, datad, datae, dataf;
       reg          upper_lut_value;
       reg          lower_lut_value;
+      reg          out_0, out_1, out_2, out_3;
       begin
          upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
          lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
-         lut6            = (dataf) ?  upper_mask_value : lower_mask_value;
+         lut6            = (dataf) ?  upper_lut_value : lower_lut_value;
       end
    endfunction // lut6
 
    assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
-
+`ifdef ADVANCED_ALM
    always @(*) begin
       if(extended_lut == "on")
         shared_lut_alm = datag;
@@ -115,6 +116,11 @@ module cyclonev_lcell_comb
       out_2 = lut4(mask_c, dataa, datab, datac, datad);
       out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
    end
+`else
+   `ifdef DEBUG
+       initial $display("Advanced ALM lut combine is not implemented yet");
+   `endif
+`endif
 endmodule // cyclonev_lcell_comb
 
 

techlibs/xilinx/cells_sim.v

@@ -30,10 +30,15 @@ module GND(output G);
 endmodule
 
 module IBUF(output O, input I);
+  parameter IOSTANDARD = "default";
+  parameter IBUF_LOW_PWR = 0;
   assign O = I;
 endmodule
 
 module OBUF(output O, input I);
+  parameter IOSTANDARD = "default";
+  parameter DRIVE = 12;
+  parameter SLEW = "SLOW";
   assign O = I;
 endmodule
 
@@ -41,6 +46,42 @@ module BUFG(output O, input I);
   assign O = I;
 endmodule
 
+module BUFGCTRL(
+    output O,
+    input I0, input I1,
+    input S0, input S1,
+    input CE0, input CE1,
+    input IGNORE0, input IGNORE1);
+
+parameter [0:0] INIT_OUT = 1'b0;
+parameter PRESELECT_I0 = "FALSE";
+parameter PRESELECT_I1 = "FALSE";
+parameter [0:0] IS_CE0_INVERTED = 1'b0;
+parameter [0:0] IS_CE1_INVERTED = 1'b0;
+parameter [0:0] IS_S0_INVERTED = 1'b0;
+parameter [0:0] IS_S1_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
+
+wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
+wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
+wire S0_true = (S0 ^ IS_S0_INVERTED);
+wire S1_true = (S1 ^ IS_S1_INVERTED);
+
+assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
+
+endmodule
+
+module BUFHCE(output O, input I, input CE);
+
+parameter [0:0] INIT_OUT = 1'b0;
+parameter CE_TYPE = "SYNC";
+parameter [0:0] IS_CE_INVERTED = 1'b0;
+
+assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
+
+endmodule
+
 // module OBUFT(output O, input I, T);
 //   assign O = T ? 1'bz : I;
 // endmodule
@@ -98,6 +139,22 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
   assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
+  parameter [63:0] INIT = 0;
+  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
+  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
+  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
+  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  assign O6 = I0 ? s1[1] : s1[0];
+
+  wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
+  wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
+  wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
+  wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
+  assign O5 = I0 ? s5_1[1] : s5_1[0];
+endmodule
+
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule

techlibs/xilinx/cells_xtra.sh

@@ -28,12 +28,12 @@ function xtract_cell_decl()
 	# xtract_cell_decl BUFG
 	xtract_cell_decl BUFGCE
 	xtract_cell_decl BUFGCE_1
-	xtract_cell_decl BUFGCTRL
+	#xtract_cell_decl BUFGCTRL
 	xtract_cell_decl BUFGMUX
 	xtract_cell_decl BUFGMUX_1
 	xtract_cell_decl BUFGMUX_CTRL
 	xtract_cell_decl BUFH
-	xtract_cell_decl BUFHCE
+	#xtract_cell_decl BUFHCE
 	xtract_cell_decl BUFIO
 	xtract_cell_decl BUFMR
 	xtract_cell_decl BUFMRCE
@@ -92,7 +92,7 @@ function xtract_cell_decl()
 	# xtract_cell_decl LUT4
 	# xtract_cell_decl LUT5
 	# xtract_cell_decl LUT6
-	xtract_cell_decl LUT6_2
+	#xtract_cell_decl LUT6_2
 	xtract_cell_decl MMCME2_ADV
 	xtract_cell_decl MMCME2_BASE
 	# xtract_cell_decl MUXF7

techlibs/xilinx/cells_xtra.v

@@ -30,29 +30,6 @@ module BUFGCE_1 (...);
     input CE, I;
 endmodule
 
-module BUFGCTRL (...);
-    output O;
-    input CE0;
-    input CE1;
-    input I0;
-    input I1;
-    input IGNORE0;
-    input IGNORE1;
-    input S0;
-    input S1;
-    parameter integer INIT_OUT = 0;
-    parameter PRESELECT_I0 = "FALSE";
-    parameter PRESELECT_I1 = "FALSE";
-    parameter [0:0] IS_CE0_INVERTED = 1'b0;
-    parameter [0:0] IS_CE1_INVERTED = 1'b0;
-    parameter [0:0] IS_I0_INVERTED = 1'b0;
-    parameter [0:0] IS_I1_INVERTED = 1'b0;
-    parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
-    parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
-    parameter [0:0] IS_S0_INVERTED = 1'b0;
-    parameter [0:0] IS_S1_INVERTED = 1'b0;
-endmodule
-
 module BUFGMUX (...);
     parameter CLK_SEL_TYPE = "SYNC";
     output O;
@@ -77,15 +54,6 @@ module BUFH (...);
     input I;
 endmodule
 
-module BUFHCE (...);
-    parameter CE_TYPE = "SYNC";
-    parameter integer INIT_OUT = 0;
-    parameter [0:0] IS_CE_INVERTED = 1'b0;
-    output O;
-    input CE;
-    input I;
-endmodule
-
 module BUFIO (...);
     output O;
     input I;
@@ -2420,12 +2388,6 @@ module LDPE (...);
     input D, G, GE, PRE;
 endmodule
 
-module LUT6_2 (...);
-    parameter [63:0] INIT = 64'h0000000000000000;
-    input I0, I1, I2, I3, I4, I5;
-    output O5, O6;
-endmodule
-
 module MMCME2_ADV (...);
     parameter BANDWIDTH = "OPTIMIZED";
     parameter real CLKFBOUT_MULT_F = 5.000;

tests/various/muxcover.ys

@@ -8,12 +8,13 @@ read_verilog -formal <<EOT
                 3'b?1?: Y = B;
                 3'b1??: Y = C;
                 3'b000: Y = D;
+                default: Y = 'bx;
             endcase
     endmodule
 EOT
 
 
-## Examle usage for "pmuxtree" and "muxcover"
+## Example usage for "pmuxtree" and "muxcover"
 
 proc
 pmuxtree
@@ -35,7 +36,7 @@ read_verilog -formal <<EOT
                 3'b010: Y = B;
                 3'b100: Y = C;
                 3'b000: Y = D;
-		default: Y = 'bx;
+                default: Y = 'bx;
             endcase
     endmodule
 EOT