mirror of https://github.com/YosysHQ/yosys.git
Add get_fsm_accept_reject for parsing SVA properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
588ce0e34a
commit
d86e875f0f
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@ -483,7 +483,7 @@ struct SvaFsm
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dnodes[state] = dnode;
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}
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SigBit getReject(SigBit *accept_sigptr = nullptr)
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void getFirstAcceptReject(SigBit *accept_p, SigBit *reject_p)
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{
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log_assert(!materialized);
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materialized = true;
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@ -525,13 +525,15 @@ struct SvaFsm
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dnodes.at(edge.first).nextstate.append(trig);
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}
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if (accept_sigptr) {
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if (accept_p) {
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for (auto &value : dnode.accept)
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accept_sig.append(module->Eq(NEW_ID, {dnode.ctrl, dnode.statesig}, {value, State::S1}));
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}
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for (auto &value : dnode.reject)
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reject_sig.append(module->Eq(NEW_ID, {dnode.ctrl, dnode.statesig}, {value, State::S1}));
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if (reject_p) {
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for (auto &value : dnode.reject)
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reject_sig.append(module->Eq(NEW_ID, {dnode.ctrl, dnode.statesig}, {value, State::S1}));
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}
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}
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for (auto &it : dnodes)
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@ -548,7 +550,7 @@ struct SvaFsm
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}
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}
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if (accept_sigptr)
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if (accept_p)
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{
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if (GetSize(accept_sig) == 0)
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final_accept_sig = State::S0;
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@ -556,17 +558,33 @@ struct SvaFsm
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final_accept_sig = accept_sig;
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else
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final_accept_sig = module->ReduceOr(NEW_ID, accept_sig);
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*accept_sigptr = final_accept_sig;
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*accept_p = final_accept_sig;
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}
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if (GetSize(reject_sig) == 0)
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final_reject_sig = State::S0;
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else if (GetSize(reject_sig) == 1)
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final_reject_sig = reject_sig;
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else
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final_reject_sig = module->ReduceOr(NEW_ID, reject_sig);
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if (reject_p)
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{
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if (GetSize(reject_sig) == 0)
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final_reject_sig = State::S0;
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else if (GetSize(reject_sig) == 1)
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final_reject_sig = reject_sig;
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else
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final_reject_sig = module->ReduceOr(NEW_ID, reject_sig);
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*reject_p = final_reject_sig;
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}
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}
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return final_reject_sig;
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SigBit getFirstAccept()
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{
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SigBit accept;
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getFirstAcceptReject(nullptr, &accept);
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return accept;
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}
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SigBit getReject()
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{
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SigBit reject;
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getFirstAcceptReject(nullptr, &reject);
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return reject;
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}
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void getDFsm(SvaFsm &output_fsm, int output_start_node, int output_accept_node, int output_reject_node)
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@ -903,20 +921,26 @@ struct VerificSvaImporter
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int sva_high = atoi(sva_high_s);
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bool sva_inf = !strcmp(sva_high_s, "$");
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int node = parse_sequence(fsm, start_node, inst->GetInput());
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Net *body_net = inst->GetInput();
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Instance *body_inst = net_to_ast_driver(body_net);
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if (body_inst != nullptr)
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parser_error(body_inst);
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int node = parse_sequence(fsm, start_node, body_net);
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for (int i = 1; i < sva_low; i++)
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{
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int next_node = fsm.createNode();
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fsm.createEdge(node, next_node);
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node = parse_sequence(fsm, next_node, inst->GetInput());
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node = parse_sequence(fsm, next_node, body_net);
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}
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if (sva_inf)
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{
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int next_node = fsm.createNode();
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fsm.createEdge(node, next_node);
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next_node = parse_sequence(fsm, next_node, inst->GetInput());
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next_node = parse_sequence(fsm, next_node, body_net);
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fsm.createLink(next_node, node);
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}
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else
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@ -925,7 +949,7 @@ struct VerificSvaImporter
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{
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int next_node = fsm.createNode();
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fsm.createEdge(node, next_node);
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next_node = parse_sequence(fsm, next_node, inst->GetInput());
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next_node = parse_sequence(fsm, next_node, body_net);
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fsm.createLink(node, next_node);
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node = next_node;
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}
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@ -974,13 +998,30 @@ struct VerificSvaImporter
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parser_error(inst);
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}
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SigBit parse_property(Net *net)
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void get_fsm_accept_reject(SvaFsm &fsm, SigBit *accept_p, SigBit *reject_p, bool swap_accpet_reject = false)
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{
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log_assert(accept_p != nullptr || reject_p != nullptr);
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if (swap_accpet_reject)
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get_fsm_accept_reject(fsm, reject_p, accept_p);
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else if (reject_p == nullptr)
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*accept_p = fsm.getAccept();
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else if (accept_p == nullptr)
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*reject_p = fsm.getReject();
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else
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fsm.getFirstAcceptReject(accept_p, reject_p);
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}
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void parse_property(Net *net, SigBit *accept_p, SigBit *reject_p)
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{
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Instance *inst = net_to_ast_driver(net);
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if (inst == nullptr)
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{
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return importer->net_map_at(net);
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if (accept_p != nullptr)
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*accept_p = importer->net_map_at(net);
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if (reject_p != nullptr)
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*reject_p = module->Not(NEW_ID, importer->net_map_at(net));
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}
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else
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if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
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@ -1012,7 +1053,7 @@ struct VerificSvaImporter
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consequent_inst = net_to_ast_driver(consequent_net);
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if (until_inst != nullptr)
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parser_error("Currently only expressions are allowed in SVA_UNTIL condition", until_inst);
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parser_error(until_inst);
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SigBit until_sig = importer->net_map_at(until_net);
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SigBit not_until_sig = module->Not(NEW_ID, until_sig);
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@ -1043,63 +1084,31 @@ struct VerificSvaImporter
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node = parse_sequence(consequent_fsm, consequent_fsm.startNode, consequent_net);
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consequent_fsm.createLink(node, consequent_fsm.acceptNode);
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SigBit prop_okay;
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if (mode_cover || mode_trigger) {
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prop_okay = consequent_not ? consequent_fsm.getReject() : consequent_fsm.getAccept();
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} else {
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SigBit consequent_match = consequent_not ? consequent_fsm.getAccept() : consequent_fsm.getReject();
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prop_okay = module->Not(NEW_ID, consequent_match);
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}
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get_fsm_accept_reject(consequent_fsm, accept_p, reject_p, consequent_not);
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if (verific_verbose) {
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log(" Consequent FSM:\n");
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consequent_fsm.dump();
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}
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return prop_okay;
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}
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else
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if (inst->Type() == PRIM_SVA_NOT)
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{
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SvaFsm fsm(clocking);
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int node = parse_sequence(fsm, fsm.startNode, inst->GetInput());
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fsm.createLink(node, fsm.acceptNode);
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SigBit prop_okay;
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if (mode_cover || mode_trigger) {
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prop_okay = fsm.getReject();
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} else {
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SigBit accept = fsm.getAccept();
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prop_okay = module->Not(NEW_ID, accept);
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}
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if (verific_verbose) {
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log(" Sequence FSM:\n");
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fsm.dump();
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}
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return prop_okay;
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}
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else
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{
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bool prop_not = inst->Type() == PRIM_SVA_NOT;
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if (prop_not) {
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net = inst->GetInput();
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inst = net_to_ast_driver(net);
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}
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SvaFsm fsm(clocking);
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int node = parse_sequence(fsm, fsm.startNode, net);
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fsm.createLink(node, fsm.acceptNode);
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SigBit prop_okay;
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if (mode_cover || mode_trigger) {
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prop_okay = fsm.getAccept();
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} else {
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SigBit accept = fsm.getReject();
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prop_okay = module->Not(NEW_ID, accept);
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}
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get_fsm_accept_reject(fsm, accept_p, reject_p, prop_not);
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if (verific_verbose) {
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log(" Sequence FSM:\n");
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fsm.dump();
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}
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return prop_okay;
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}
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}
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@ -1124,35 +1133,39 @@ struct VerificSvaImporter
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// parse SVA sequence into trigger signal
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Net *net = clocking.body_net;
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SigBit prop_okay = parse_property(net);
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SigBit accept_bit = State::S0, reject_bit = State::S0;
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if (mode_assert || mode_assume) {
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parse_property(net, nullptr, &reject_bit);
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} else {
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parse_property(net, &accept_bit, nullptr);
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}
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if (mode_trigger)
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{
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module->connect(importer->net_map_at(root->GetOutput()), prop_okay);
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module->connect(importer->net_map_at(root->GetOutput()), accept_bit);
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}
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else
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{
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SigBit sig_a = module->Not(NEW_ID, reject_bit);
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SigBit sig_en = module->Or(NEW_ID, accept_bit, reject_bit);
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// add final FF stage
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SigBit prop_okay_q = module->addWire(NEW_ID);
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clocking.addDff(NEW_ID, prop_okay, prop_okay_q, Const(mode_cover ? 0 : 1, 1));
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SigBit sig_a_q = module->addWire(NEW_ID);
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SigBit sig_en_q = module->addWire(NEW_ID);
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clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0);
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clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
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// generate assert/assume/cover cell
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RTLIL::Cell *c = nullptr;
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if (eventually) {
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parser_error("No support for eventually in Verific SVA bindings yet", root);
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// if (mode_assert) c = module->addLive(root_name, prop_okay_q, prop_start_q);
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// if (mode_assume) c = module->addFair(root_name, prop_okay_q, prop_start_q);
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} else {
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if (mode_assert) c = module->addAssert(root_name, prop_okay_q, State::S1);
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if (mode_assume) c = module->addAssume(root_name, prop_okay_q, State::S1);
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if (mode_cover) c = module->addCover(root_name, prop_okay_q, State::S1);
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}
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if (mode_assert) c = module->addAssert(root_name, sig_a_q, sig_en_q);
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if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q);
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if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q);
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if (c != nullptr)
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importer->import_attributes(c->attributes, root);
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importer->import_attributes(c->attributes, root);
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}
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}
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catch (ParserErrorException)
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