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Revert synth_xilinx 'fine' label more to how it used to be...

This commit is contained in:
Eddie Hung 2019-04-26 16:53:16 -07:00
parent ea0e0722bb
commit d855683917
1 changed files with 40 additions and 21 deletions
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59
techlibs/xilinx/synth_xilinx.cc
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@ -108,23 +108,23 @@ struct SynthXilinxPass : public Pass
log(" techmap -map +/xilinx/drams_map.v\n");
log("\n");
log(" fine:\n");
log(" opt -fast\n");
log(" opt -fast -full\n");
log(" memory_map\n");
log(" dffsr2dff\n");
log(" dff2dffe\n");
log(" techmap -map +/xilinx/arith_map.v\n");
log(" pmux2shiftx (without '-nosrl' only)\n");
log(" opt -full\n");
log(" techmap\n");
log(" opt -fast\n");
log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
log(" opt -fast\n");
log("\n");
log(" map_cells:\n");
log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
log(" pmux2shiftx (without '-nosrl' only)\n");
log(" opt_expr -mux_undef (without '-nosrl' only)\n");
log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
log(" techmap -map +/xilinx/cells_map.v\n");
log(" clean\n");
log("\n");
log(" map_luts:\n");
log(" opt -full\n");
log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
log(" clean\n");
@ -262,9 +262,30 @@ struct SynthXilinxPass : public Pass
}
}
log(" fine:\n");
log(" opt -fast -full\n");
log(" memory_map\n");
log(" dffsr2dff\n");
log(" dff2dffe\n");
log(" techmap -map +/xilinx/arith_map.v\n");
log(" pmux2shiftx (without '-nosrl' only)\n");
log(" opt -full\n");
log(" techmap\n");
log(" opt -fast\n");
log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
log(" opt -fast\n");
log("\n");
log(" map_cells:\n");
log(" techmap -map +/xilinx/cells_map.v\n");
log(" clean\n");
log("\n");
log(" map_luts:\n");
log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
if (check_label(active, run_from, run_to, "fine"))
{
Pass::call(design, "opt -fast");
Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe");
@ -275,25 +296,24 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "techmap -map +/xilinx/arith_map.v");
}
Pass::call(design, "opt -full");
Pass::call(design, "techmap");
Pass::call(design, "opt -fast");
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifiying variable-length shift registers,
// so attempt to convert $pmux-es to the former
if (!nosrl)
Pass::call(design, "pmux2shiftx");
Pass::call(design, "opt -fast");
}
if (check_label(active, run_from, run_to, "map_cells"))
{
if (!nosrl) {
// shregmap operates on bit-level flops, not word-level,
// so break those down here
Pass::call(design, "simplemap t:$dff t:$dffe");
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifiying variable-length shift registers,
// so attempt to convert $pmux-es to the former
Pass::call(design, "pmux2shiftx");
// pmux2shiftx can leave behind a $pmux with a single entry
// -- need this to clean that up before shregmap
Pass::call(design, "opt_expr -mux_undef");
// shregmap with '-tech xilinx' infers variable length shift regs
if (!nosrl)
Pass::call(design, "shregmap -tech xilinx -minlen 3");
}
Pass::call(design, "techmap -map +/xilinx/cells_map.v");
Pass::call(design, "clean");
@ -301,7 +321,6 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");