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More conservastive $eq/$ne/$eqx/$nex opt_const code

This commit is contained in:
Clifford Wolf 2013-12-28 10:29:22 +01:00
parent 122b3c067b
commit d81e3ed3ae
1 changed files with 2 additions and 8 deletions
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10
passes/opt/opt_const.cc
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@ -160,19 +160,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assert(a.chunks.size() == b.chunks.size()); assert(a.chunks.size() == b.chunks.size());
for (size_t i = 0; i < a.chunks.size(); i++) { for (size_t i = 0; i < a.chunks.size(); i++) {
if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0] &&
a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0]) { a.chunks[i].data.bits[0] <= RTLIL::State::S1 && b.chunks[i].data.bits[0] <= RTLIL::State::S1) {
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(module, cell, "empty", "\\Y", new_y); replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell; goto next_cell;
} }
if (cell->type == "$eq" || cell->type == "$ne") {
if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
}
if (a.chunks[i] == b.chunks[i]) if (a.chunks[i] == b.chunks[i])
continue; continue;
new_a.append(a.chunks[i]); new_a.append(a.chunks[i]);