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Cleaned verilog code from not used defines

This commit is contained in:
Miodrag Milanovic 2019-10-04 08:45:58 +02:00
parent abb5a3a44d
commit d6ef9b1a6b
1 changed files with 0 additions and 6 deletions
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6
tests/ecp5/shifter.v
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@ -9,14 +9,8 @@ in
always @(posedge clk) always @(posedge clk)
begin begin
`ifndef BUG
out <= out >> 1; out <= out >> 1;
out[7] <= in; out[7] <= in;
`else
out <= out << 1;
out[7] <= in;
`endif
end end
endmodule endmodule