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verific : VHDL assert DFF initial value set on Verific library patch side

This commit is contained in:
Miodrag Milanovic 2024-11-21 13:43:26 +01:00
parent 4b3c03dabc
commit d6bd521487
1 changed files with 0 additions and 6 deletions
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6
frontends/verific/verific.cc
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@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log(" assert condition %s.\n", log_signal(cond)); log(" assert condition %s.\n", log_signal(cond));
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1); Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst); import_attributes(cell->attributes, inst);
continue; continue;
} }