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Removing trailing whitespace

This commit is contained in:
diego 2020-06-10 10:35:40 -05:00
parent 3c2a1171ff
commit d68a8f9e2b
1 changed files with 30 additions and 30 deletions
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60
tests/various/dynamic_part_select.ys
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@ -3,105 +3,105 @@ read_verilog ./dynamic_part_select/original.v
proc proc
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/original_gate.v read_verilog ./dynamic_part_select/original_gate.v
proc proc
rename -top gate rename -top gate
design -stash gate design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Multiple blocking assingments ### ### Multiple blocking assingments ###
design -reset design -reset
read_verilog ./dynamic_part_select/multiple_blocking.v read_verilog ./dynamic_part_select/multiple_blocking.v
proc proc
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/multiple_blocking_gate.v read_verilog ./dynamic_part_select/multiple_blocking_gate.v
proc proc
rename -top gate rename -top gate
design -stash gate design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Non-blocking to the same output register ### ### Non-blocking to the same output register ###
design -reset design -reset
read_verilog ./dynamic_part_select/nonblocking.v read_verilog ./dynamic_part_select/nonblocking.v
proc proc
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/nonblocking_gate.v read_verilog ./dynamic_part_select/nonblocking_gate.v
proc proc
rename -top gate rename -top gate
design -stash gate design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### For-loop select, one dynamic input ### For-loop select, one dynamic input
design -reset design -reset
read_verilog ./dynamic_part_select/forloop_select.v read_verilog ./dynamic_part_select/forloop_select.v
proc proc
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/forloop_select_gate.v read_verilog ./dynamic_part_select/forloop_select_gate.v
proc proc
rename -top gate rename -top gate
design -stash gate design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
#### Double loop (part-select, reset) ### #### Double loop (part-select, reset) ###
design -reset design -reset
read_verilog ./dynamic_part_select/reset_test.v read_verilog ./dynamic_part_select/reset_test.v
proc proc
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/reset_test_gate.v read_verilog ./dynamic_part_select/reset_test_gate.v
proc proc
rename -top gate rename -top gate
design -stash gate design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
### Reversed part-select case ### ### Reversed part-select case ###
design -reset design -reset
read_verilog ./dynamic_part_select/reversed.v read_verilog ./dynamic_part_select/reversed.v
proc proc
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/reversed_gate.v read_verilog ./dynamic_part_select/reversed_gate.v
proc proc
rename -top gate rename -top gate
design -stash gate design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
@ -120,8 +120,8 @@ design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -show-public -verify -set-init-zero equiv sat -prove-asserts -show-public -verify -set-init-zero equiv
### ###
@ -139,8 +139,8 @@ design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -falsify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -falsify -set-init-zero equiv
## Part select + latch, with no shift&mask ## Part select + latch, with no shift&mask
@ -157,6 +157,6 @@ design -stash gate
design -copy-from gold -as gold gold design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv