mirror of https://github.com/YosysHQ/yosys.git
xaiger: do not derive cells
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721040df76
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d64df21630
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@ -248,6 +248,7 @@ struct XAigerWriter
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auto it = cell->attributes.find(ID::abc9_box_seq);
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if (it != cell->attributes.end()) {
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log_assert(!cell->has_keep_attr());
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log_assert(cell->parameters.empty());
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int abc9_box_seq = it->second.as_int();
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if (GetSize(box_list) <= abc9_box_seq)
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box_list.resize(abc9_box_seq+1);
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@ -260,13 +261,6 @@ struct XAigerWriter
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continue;
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}
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if (!cell->parameters.empty()) {
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auto derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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log_assert(inst_module->get_blackbox_attribute());
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}
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if (!timing.count(inst_module->name))
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timing.setup_module(inst_module);
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auto &t = timing.at(inst_module->name).arrival;
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