riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

xaiger: do not derive cells

This commit is contained in:
Eddie Hung 2020-05-24 08:17:30 -07:00
parent 721040df76
commit d64df21630
1 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
backends/aiger/xaiger.cc
View File

@ -248,6 +248,7 @@ struct XAigerWriter
auto it = cell->attributes.find(ID::abc9_box_seq); auto it = cell->attributes.find(ID::abc9_box_seq);
if (it != cell->attributes.end()) { if (it != cell->attributes.end()) {
log_assert(!cell->has_keep_attr()); log_assert(!cell->has_keep_attr());
log_assert(cell->parameters.empty());
int abc9_box_seq = it->second.as_int(); int abc9_box_seq = it->second.as_int();
if (GetSize(box_list) <= abc9_box_seq) if (GetSize(box_list) <= abc9_box_seq)
box_list.resize(abc9_box_seq+1); box_list.resize(abc9_box_seq+1);
@ -260,13 +261,6 @@ struct XAigerWriter
continue; continue;
} }
if (!cell->parameters.empty()) {
auto derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
log_assert(inst_module);
log_assert(inst_module->get_blackbox_attribute());
}
if (!timing.count(inst_module->name)) if (!timing.count(inst_module->name))
timing.setup_module(inst_module); timing.setup_module(inst_module);
auto &t = timing.at(inst_module->name).arrival; auto &t = timing.at(inst_module->name).arrival;