From d640157ec4b4574f5bda6a10d2f6ddec6ee09585 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Wed, 15 Jan 2025 15:56:42 +0100 Subject: [PATCH] fix some cases of hdlname being added to objects with private names --- frontends/verific/verific.cc | 3 ++- passes/fsm/fsm_extract.cc | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8f1b07b10..cdd0ed802 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1464,7 +1464,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } import_attributes(module->attributes, nl, nl); - module->set_string_attribute(ID::hdlname, nl->CellBaseName()); + if (module->name.isPublic()) + module->set_string_attribute(ID::hdlname, nl->CellBaseName()); module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name()); #ifdef VERIFIC_VHDL_SUPPORT if (nl->IsFromVhdl()) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 6114dd34b..17675b402 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -377,6 +377,10 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->setPort(ID::CTRL_OUT, ctrl_out); fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str()); fsm_cell->attributes = wire->attributes; + if(fsm_cell->attributes.count(ID::hdlname)) { + fsm_cell->attributes[ID(scopename)] = fsm_cell->attributes[ID::hdlname]; + fsm_cell->attributes.erase(ID::hdlname); + } fsm_data.copy_to_cell(fsm_cell); // rename original state wire @@ -385,6 +389,10 @@ static void extract_fsm(RTLIL::Wire *wire) wire->attributes.erase(ID::fsm_encoding); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); module->wires_[wire->name] = wire; + if(wire->attributes.count(ID::hdlname)) { + wire->attributes[ID(scopename)] = wire->attributes[ID::hdlname]; + wire->attributes.erase(ID::hdlname); + } // unconnect control outputs from old drivers