mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: Convert to Mem helpers.
This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
This commit is contained in:
Marcelina Kościelnicka
parent
7f12820b26
commit
d5c9595668
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@ -216,7 +216,7 @@ bool is_internal_cell(RTLIL::IdString type)
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bool is_effectful_cell(RTLIL::IdString type)
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{
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return type == ID($memwr) || type.isPublic();
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return type.isPublic();
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}
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bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
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@ -274,12 +274,16 @@ struct FlowGraph {
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CELL_EVAL,
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PROCESS_SYNC,
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PROCESS_CASE,
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MEM_RDPORT,
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MEM_WRPORTS,
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};
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Type type;
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RTLIL::SigSig connect = {};
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const RTLIL::Cell *cell = NULL;
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const RTLIL::Process *process = NULL;
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const RTLIL::Cell *cell = nullptr;
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const RTLIL::Process *process = nullptr;
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const Mem *mem = nullptr;
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int portidx;
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};
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std::vector<Node*> nodes;
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@ -414,7 +418,7 @@ struct FlowGraph {
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if (cell->output(conn.first)) {
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if (is_inlinable_cell(cell->type))
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add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true);
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else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
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else if (is_ff_cell(cell->type))
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add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false);
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else if (is_internal_cell(cell->type))
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add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
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@ -502,6 +506,49 @@ struct FlowGraph {
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add_case_rule_defs_uses(node, &process->root_case);
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return node;
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}
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// Memories
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void add_node(const Mem *mem) {
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for (int i = 0; i < GetSize(mem->rd_ports); i++) {
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auto &port = mem->rd_ports[i];
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Node *node = new Node;
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node->type = Node::Type::MEM_RDPORT;
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node->mem = mem;
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node->portidx = i;
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nodes.push_back(node);
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add_defs(node, port.data, /*is_ff=*/port.clk_enable, /*inlinable=*/false);
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add_uses(node, port.clk);
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add_uses(node, port.en);
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add_uses(node, port.arst);
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add_uses(node, port.srst);
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add_uses(node, port.addr);
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if (port.transparent && port.clk_enable) {
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// Our implementation of transparent read ports reads en, addr and data from every write port
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// in the same domain.
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for (auto &wrport : mem->wr_ports) {
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if (wrport.clk_enable && wrport.clk == port.clk && wrport.clk_polarity == port.clk_polarity) {
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add_uses(node, wrport.en);
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add_uses(node, wrport.addr);
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add_uses(node, wrport.data);
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}
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}
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// Also we read the address twice in this case (prevent inlining).
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add_uses(node, port.addr);
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}
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}
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if (!mem->wr_ports.empty()) {
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Node *node = new Node;
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node->type = Node::Type::MEM_WRPORTS;
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node->mem = mem;
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nodes.push_back(node);
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for (auto &port : mem->wr_ports) {
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add_uses(node, port.clk);
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add_uses(node, port.en);
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add_uses(node, port.addr);
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add_uses(node, port.data);
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}
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}
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}
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};
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std::vector<std::string> split_by(const std::string &str, const std::string &sep)
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@ -637,10 +684,9 @@ struct CxxrtlWorker {
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int temporary = 0;
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dict<const RTLIL::Module*, SigMap> sigmaps;
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dict<const RTLIL::Module*, std::vector<Mem>> mod_memories;
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pool<const RTLIL::Wire*> edge_wires;
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dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
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pool<const RTLIL::Memory*> writable_memories;
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dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
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dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule, debug_schedule;
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dict<const RTLIL::Wire*, WireType> wire_types, debug_wire_types;
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dict<RTLIL::SigBit, bool> bit_has_state;
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@ -724,9 +770,9 @@ struct CxxrtlWorker {
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return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox)));
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}
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std::string mangle(const RTLIL::Memory *memory)
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std::string mangle(const Mem *mem)
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{
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return mangle_memory_name(memory->name);
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return mangle_memory_name(mem->memid);
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}
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std::string mangle(const RTLIL::Cell *cell)
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@ -1216,114 +1262,6 @@ struct CxxrtlWorker {
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dump_sigspec_rhs(cell->getPort(ID::CLR));
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f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
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}
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// Memory ports
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} else if (cell->type.in(ID($memrd), ID($memwr))) {
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if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
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log_assert(!for_debug);
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RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
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clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
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if (clk_bit.wire) {
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f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
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<< mangle(clk_bit) << ") {\n";
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} else {
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f << indent << "if (false) {\n";
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}
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inc_indent();
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}
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RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
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std::string valid_index_temp = fresh_temporary();
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f << indent << "auto " << valid_index_temp << " = memory_index(";
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// Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous
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// memory read ports can.
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dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug);
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f << ", " << memory->start_offset << ", " << memory->size << ");\n";
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if (cell->type == ID($memrd)) {
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bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
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if (has_enable) {
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << ") {\n";
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inc_indent();
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}
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// The generated code has two bounds checks; one in an assertion, and another that guards the read.
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// This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
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// loudly crashes if an illegal condition is encountered. The assert may be turned off with -DCXXRTL_NDEBUG
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// not only for release builds, but also to make sure the simulator (which is presumably embedded in some
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// larger program) will never crash the code that calls into it.
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//
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// If assertions are disabled, out of bounds reads are defined to return zero.
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f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
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f << indent << "if(" << valid_index_temp << ".valid) {\n";
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inc_indent();
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if (writable_memories[memory]) {
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std::string lhs_temp = fresh_temporary();
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f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
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<< mangle(memory) << "[" << valid_index_temp << ".index];\n";
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std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
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if (!memwr_cells.empty()) {
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std::string addr_temp = fresh_temporary();
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f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
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dump_sigspec_rhs(cell->getPort(ID::ADDR));
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f << ";\n";
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std::sort(memwr_cells.begin(), memwr_cells.end(),
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[](const RTLIL::Cell *a, const RTLIL::Cell *b) {
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return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
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});
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for (auto memwr_cell : memwr_cells) {
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f << indent << "if (" << addr_temp << " == ";
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dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
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f << ") {\n";
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inc_indent();
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f << indent << lhs_temp << " = " << lhs_temp;
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f << ".update(";
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dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
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f << ", ";
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dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
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f << ");\n";
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dec_indent();
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f << indent << "}\n";
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}
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}
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID::DATA));
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f << " = " << lhs_temp << ";\n";
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} else {
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID::DATA));
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f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
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}
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dec_indent();
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f << indent << "} else {\n";
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inc_indent();
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f << indent;
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dump_sigspec_lhs(cell->getPort(ID::DATA));
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f << " = value<" << memory->width << "> {};\n";
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dec_indent();
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f << indent << "}\n";
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if (has_enable) {
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dec_indent();
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f << indent << "}\n";
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}
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} else /*if (cell->type == ID($memwr))*/ {
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log_assert(writable_memories[memory]);
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// See above for rationale of having both the assert and the condition.
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//
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// If assertions are disabled, out of bounds writes are defined to do nothing.
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f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
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f << indent << "if (" << valid_index_temp << ".valid) {\n";
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inc_indent();
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f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
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dump_sigspec_rhs(cell->getPort(ID::DATA));
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f << ", ";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
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dec_indent();
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f << indent << "}\n";
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}
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if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
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dec_indent();
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f << indent << "}\n";
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}
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// Internal cells
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} else if (is_internal_cell(cell->type)) {
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log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
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@ -1567,6 +1505,161 @@ struct CxxrtlWorker {
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}
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}
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void dump_mem_rdport(const Mem *mem, int portidx, bool for_debug = false)
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{
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auto &port = mem->rd_ports[portidx];
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dump_attrs(&port);
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f << indent << "// memory " << mem->memid.str() << " read port " << portidx << "\n";
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if (port.clk_enable) {
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log_assert(!for_debug);
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RTLIL::SigBit clk_bit = port.clk[0];
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clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
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if (clk_bit.wire) {
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f << indent << "if (" << (port.clk_polarity ? "posedge_" : "negedge_")
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<< mangle(clk_bit) << ") {\n";
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} else {
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f << indent << "if (false) {\n";
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}
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inc_indent();
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}
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std::vector<const RTLIL::Cell*> inlined_cells_addr;
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collect_sigspec_rhs(port.addr, for_debug, inlined_cells_addr);
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if (!inlined_cells_addr.empty())
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dump_inlined_cells(inlined_cells_addr);
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std::string valid_index_temp = fresh_temporary();
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f << indent << "auto " << valid_index_temp << " = memory_index(";
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// Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous
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// memory read ports can.
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dump_sigspec_rhs(port.addr, for_debug);
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f << ", " << mem->start_offset << ", " << mem->size << ");\n";
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bool has_enable = port.clk_enable && !port.en.is_fully_ones();
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if (has_enable) {
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std::vector<const RTLIL::Cell*> inlined_cells_en;
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collect_sigspec_rhs(port.en, for_debug, inlined_cells_en);
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if (!inlined_cells_en.empty())
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dump_inlined_cells(inlined_cells_en);
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f << indent << "if (";
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dump_sigspec_rhs(port.en);
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f << ") {\n";
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inc_indent();
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}
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// The generated code has two bounds checks; one in an assertion, and another that guards the read.
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// This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless
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// loudly crashes if an illegal condition is encountered. The assert may be turned off with -DCXXRTL_NDEBUG
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// not only for release builds, but also to make sure the simulator (which is presumably embedded in some
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// larger program) will never crash the code that calls into it.
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//
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// If assertions are disabled, out of bounds reads are defined to return zero.
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f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n";
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f << indent << "if(" << valid_index_temp << ".valid) {\n";
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inc_indent();
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if (!mem->wr_ports.empty()) {
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std::string lhs_temp = fresh_temporary();
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f << indent << "value<" << mem->width << "> " << lhs_temp << " = "
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<< mangle(mem) << "[" << valid_index_temp << ".index];\n";
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if (port.transparent && port.clk_enable) {
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std::string addr_temp = fresh_temporary();
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f << indent << "const value<" << port.addr.size() << "> &" << addr_temp << " = ";
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dump_sigspec_rhs(port.addr);
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f << ";\n";
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for (auto &wrport : mem->wr_ports) {
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if (!wrport.clk_enable)
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continue;
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if (wrport.clk != port.clk)
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continue;
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if (wrport.clk_polarity != port.clk_polarity)
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continue;
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f << indent << "if (" << addr_temp << " == ";
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dump_sigspec_rhs(wrport.addr);
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f << ") {\n";
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inc_indent();
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f << indent << lhs_temp << " = " << lhs_temp;
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f << ".update(";
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dump_sigspec_rhs(wrport.data);
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f << ", ";
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dump_sigspec_rhs(wrport.en);
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f << ");\n";
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dec_indent();
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f << indent << "}\n";
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}
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}
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f << indent;
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dump_sigspec_lhs(port.data);
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f << " = " << lhs_temp << ";\n";
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} else {
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f << indent;
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dump_sigspec_lhs(port.data);
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f << " = " << mangle(mem) << "[" << valid_index_temp << ".index];\n";
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}
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dec_indent();
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f << indent << "} else {\n";
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inc_indent();
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f << indent;
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dump_sigspec_lhs(port.data);
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f << " = value<" << mem->width << "> {};\n";
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dec_indent();
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f << indent << "}\n";
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if (has_enable) {
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dec_indent();
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f << indent << "}\n";
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}
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if (port.clk_enable) {
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dec_indent();
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f << indent << "}\n";
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}
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}
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void dump_mem_wrports(const Mem *mem, bool for_debug = false)
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{
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log_assert(!for_debug);
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for (int portidx = 0; portidx < GetSize(mem->wr_ports); portidx++) {
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auto &port = mem->wr_ports[portidx];
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dump_attrs(&port);
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f << indent << "// memory " << mem->memid.str() << " write port " << portidx << "\n";
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if (port.clk_enable) {
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RTLIL::SigBit clk_bit = port.clk[0];
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clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
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if (clk_bit.wire) {
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f << indent << "if (" << (port.clk_polarity ? "posedge_" : "negedge_")
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<< mangle(clk_bit) << ") {\n";
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} else {
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f << indent << "if (false) {\n";
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}
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inc_indent();
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}
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std::vector<const RTLIL::Cell*> inlined_cells_addr;
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collect_sigspec_rhs(port.addr, for_debug, inlined_cells_addr);
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if (!inlined_cells_addr.empty())
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dump_inlined_cells(inlined_cells_addr);
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std::string valid_index_temp = fresh_temporary();
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f << indent << "auto " << valid_index_temp << " = memory_index(";
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dump_sigspec_rhs(port.addr);
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f << ", " << mem->start_offset << ", " << mem->size << ");\n";
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// See above for rationale of having both the assert and the condition.
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//
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// If assertions are disabled, out of bounds writes are defined to do nothing.
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f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n";
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f << indent << "if (" << valid_index_temp << ".valid) {\n";
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inc_indent();
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std::vector<const RTLIL::Cell*> inlined_cells;
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collect_sigspec_rhs(port.data, for_debug, inlined_cells);
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collect_sigspec_rhs(port.en, for_debug, inlined_cells);
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if (!inlined_cells.empty())
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dump_inlined_cells(inlined_cells);
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f << indent << mangle(mem) << ".update(" << valid_index_temp << ".index, ";
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dump_sigspec_rhs(port.data);
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f << ", ";
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dump_sigspec_rhs(port.en);
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f << ", " << portidx << ");\n";
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dec_indent();
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f << indent << "}\n";
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if (port.clk_enable) {
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dec_indent();
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f << indent << "}\n";
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}
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}
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}
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void dump_wire(const RTLIL::Wire *wire, bool is_local)
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{
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const auto &wire_type = wire_types[wire];
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@ -1650,41 +1743,28 @@ struct CxxrtlWorker {
|
|||
f << "value<" << wire->width << "> " << mangle(wire) << ";\n";
|
||||
}
|
||||
|
||||
void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory)
|
||||
void dump_memory(Mem *mem)
|
||||
{
|
||||
vector<const RTLIL::Cell*> init_cells;
|
||||
for (auto cell : module->cells())
|
||||
if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
|
||||
init_cells.push_back(cell);
|
||||
|
||||
std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
|
||||
int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
|
||||
int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
|
||||
return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
|
||||
});
|
||||
|
||||
dump_attrs(memory);
|
||||
f << indent << "memory<" << memory->width << "> " << mangle(memory)
|
||||
<< " { " << memory->size << "u";
|
||||
if (init_cells.empty()) {
|
||||
dump_attrs(mem);
|
||||
f << indent << "memory<" << mem->width << "> " << mangle(mem)
|
||||
<< " { " << mem->size << "u";
|
||||
if (!GetSize(mem->inits)) {
|
||||
f << " };\n";
|
||||
} else {
|
||||
f << ",\n";
|
||||
inc_indent();
|
||||
for (auto cell : init_cells) {
|
||||
dump_attrs(cell);
|
||||
RTLIL::Const data = cell->getPort(ID::DATA).as_const();
|
||||
size_t width = cell->getParam(ID::WIDTH).as_int();
|
||||
size_t words = cell->getParam(ID::WORDS).as_int();
|
||||
f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
|
||||
<< stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
|
||||
for (auto &init : mem->inits) {
|
||||
dump_attrs(&init);
|
||||
int words = GetSize(init.data) / mem->width;
|
||||
f << indent << "memory<" << mem->width << ">::init<" << words << "> { "
|
||||
<< stringf("%#x", init.addr.as_int()) << ", {";
|
||||
inc_indent();
|
||||
for (size_t n = 0; n < words; n++) {
|
||||
for (int n = 0; n < words; n++) {
|
||||
if (n % 4 == 0)
|
||||
f << "\n" << indent;
|
||||
else
|
||||
f << " ";
|
||||
dump_const(data, width, n * width, /*fixed_width=*/true);
|
||||
dump_const(init.data, mem->width, n * mem->width, /*fixed_width=*/true);
|
||||
f << ",";
|
||||
}
|
||||
dec_indent();
|
||||
|
|
@ -1735,6 +1815,12 @@ struct CxxrtlWorker {
|
|||
case FlowGraph::Node::Type::PROCESS_SYNC:
|
||||
dump_process_syncs(node.process);
|
||||
break;
|
||||
case FlowGraph::Node::Type::MEM_RDPORT:
|
||||
dump_mem_rdport(node.mem, node.portidx);
|
||||
break;
|
||||
case FlowGraph::Node::Type::MEM_WRPORTS:
|
||||
dump_mem_wrports(node.mem);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1764,6 +1850,12 @@ struct CxxrtlWorker {
|
|||
case FlowGraph::Node::Type::PROCESS_SYNC:
|
||||
dump_process_syncs(node.process, /*for_debug=*/true);
|
||||
break;
|
||||
case FlowGraph::Node::Type::MEM_RDPORT:
|
||||
dump_mem_rdport(node.mem, node.portidx, /*for_debug=*/true);
|
||||
break;
|
||||
case FlowGraph::Node::Type::MEM_WRPORTS:
|
||||
dump_mem_wrports(node.mem, /*for_debug=*/true);
|
||||
break;
|
||||
default:
|
||||
log_abort();
|
||||
}
|
||||
|
|
@ -1783,10 +1875,10 @@ struct CxxrtlWorker {
|
|||
f << indent << "if (" << mangle(wire) << ".commit()) changed = true;\n";
|
||||
}
|
||||
if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
|
||||
for (auto memory : module->memories) {
|
||||
if (!writable_memories[memory.second])
|
||||
for (auto &mem : mod_memories[module]) {
|
||||
if (!GetSize(mem.wr_ports))
|
||||
continue;
|
||||
f << indent << "if (" << mangle(memory.second) << ".commit()) changed = true;\n";
|
||||
f << indent << "if (" << mangle(&mem) << ".commit()) changed = true;\n";
|
||||
}
|
||||
for (auto cell : module->cells()) {
|
||||
if (is_internal_cell(cell->type))
|
||||
|
|
@ -1928,12 +2020,12 @@ struct CxxrtlWorker {
|
|||
}
|
||||
}
|
||||
if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
|
||||
for (auto &memory_it : module->memories) {
|
||||
if (!memory_it.first.isPublic())
|
||||
for (auto &mem : mod_memories[module]) {
|
||||
if (!mem.memid.isPublic())
|
||||
continue;
|
||||
f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
|
||||
f << ", debug_item(" << mangle(memory_it.second) << ", ";
|
||||
f << memory_it.second->start_offset << "));\n";
|
||||
f << indent << "items.add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
|
||||
f << ", debug_item(" << mangle(&mem) << ", ";
|
||||
f << mem.start_offset << "));\n";
|
||||
}
|
||||
for (auto cell : module->cells()) {
|
||||
if (is_internal_cell(cell->type))
|
||||
|
|
@ -2048,8 +2140,8 @@ struct CxxrtlWorker {
|
|||
for (auto wire : module->wires())
|
||||
dump_debug_wire(wire, /*is_local=*/false);
|
||||
bool has_memories = false;
|
||||
for (auto memory : module->memories) {
|
||||
dump_memory(module, memory.second);
|
||||
for (auto &mem : mod_memories[module]) {
|
||||
dump_memory(&mem);
|
||||
has_memories = true;
|
||||
}
|
||||
if (has_memories)
|
||||
|
|
@ -2313,6 +2405,11 @@ struct CxxrtlWorker {
|
|||
SigMap &sigmap = sigmaps[module];
|
||||
sigmap.set(module);
|
||||
|
||||
std::vector<Mem> &memories = mod_memories[module];
|
||||
memories = Mem::get_all_memories(module);
|
||||
for (auto &mem : memories)
|
||||
mem.narrow();
|
||||
|
||||
if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
|
||||
for (auto port : module->ports) {
|
||||
RTLIL::Wire *wire = module->wire(port);
|
||||
|
|
@ -2357,13 +2454,13 @@ struct CxxrtlWorker {
|
|||
for (auto conn : module->connections())
|
||||
flow.add_node(conn);
|
||||
|
||||
dict<const RTLIL::Cell*, FlowGraph::Node*> memrw_cell_nodes;
|
||||
dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
|
||||
pool<const RTLIL::Cell*>> memwr_per_domain;
|
||||
for (auto cell : module->cells()) {
|
||||
if (!cell->known())
|
||||
log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
|
||||
|
||||
if (cell->is_mem_cell())
|
||||
continue;
|
||||
|
||||
RTLIL::Module *cell_module = design->module(cell->type);
|
||||
if (cell_module &&
|
||||
cell_module->get_blackbox_attribute() &&
|
||||
|
|
@ -2375,7 +2472,7 @@ struct CxxrtlWorker {
|
|||
cell_module->get_bool_attribute(ID(cxxrtl_template)))
|
||||
blackbox_specializations[cell_module].insert(template_args(cell));
|
||||
|
||||
FlowGraph::Node *node = flow.add_node(cell);
|
||||
flow.add_node(cell);
|
||||
|
||||
// Various DFF cells are treated like posedge/negedge processes, see above for details.
|
||||
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
|
||||
|
|
@ -2383,43 +2480,23 @@ struct CxxrtlWorker {
|
|||
register_edge_signal(sigmap, cell->getPort(ID::CLK),
|
||||
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
|
||||
}
|
||||
// Similar for memory port cells.
|
||||
if (cell->type.in(ID($memrd), ID($memwr))) {
|
||||
if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
|
||||
if (is_valid_clock(cell->getPort(ID::CLK)))
|
||||
register_edge_signal(sigmap, cell->getPort(ID::CLK),
|
||||
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
|
||||
}
|
||||
memrw_cell_nodes[cell] = node;
|
||||
}
|
||||
// Optimize access to read-only memories.
|
||||
if (cell->type == ID($memwr))
|
||||
writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
|
||||
// Collect groups of memory write ports in the same domain.
|
||||
if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && is_valid_clock(cell->getPort(ID::CLK))) {
|
||||
RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
|
||||
const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
|
||||
memwr_per_domain[{clk_bit, memory}].insert(cell);
|
||||
}
|
||||
// Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
|
||||
// of RTLIL memory objects and $memrd/$memwr/$meminit cells.
|
||||
if (cell->type.in(ID($mem)))
|
||||
log_assert(false);
|
||||
}
|
||||
for (auto cell : module->cells()) {
|
||||
// Collect groups of memory write ports read by every transparent read port.
|
||||
if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && is_valid_clock(cell->getPort(ID::CLK)) &&
|
||||
cell->getParam(ID::TRANSPARENT).as_bool()) {
|
||||
RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
|
||||
const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
|
||||
for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
|
||||
transparent_for[cell].insert(memwr_cell);
|
||||
// Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
|
||||
// in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
|
||||
flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
|
||||
flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
|
||||
flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
|
||||
}
|
||||
|
||||
for (auto &mem : memories) {
|
||||
flow.add_node(&mem);
|
||||
|
||||
// Clocked memory cells are treated like posedge/negedge processes as well.
|
||||
for (auto &port : mem.rd_ports) {
|
||||
if (port.clk_enable)
|
||||
if (is_valid_clock(port.clk))
|
||||
register_edge_signal(sigmap, port.clk,
|
||||
port.clk_polarity ? RTLIL::STp : RTLIL::STn);
|
||||
}
|
||||
for (auto &port : mem.wr_ports) {
|
||||
if (port.clk_enable)
|
||||
if (is_valid_clock(port.clk))
|
||||
register_edge_signal(sigmap, port.clk,
|
||||
port.clk_polarity ? RTLIL::STp : RTLIL::STn);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2518,6 +2595,8 @@ struct CxxrtlWorker {
|
|||
for (auto node : flow.nodes) {
|
||||
if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type))
|
||||
worklist.insert(node); // node has effects
|
||||
else if (node->type == FlowGraph::Node::Type::MEM_WRPORTS)
|
||||
worklist.insert(node); // node is memory write
|
||||
else if (flow.node_sync_defs.count(node))
|
||||
worklist.insert(node); // node is a flip-flop
|
||||
else if (flow.node_comb_defs.count(node)) {
|
||||
|
|
@ -2747,9 +2826,9 @@ struct CxxrtlWorker {
|
|||
}
|
||||
}
|
||||
|
||||
void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init, bool &has_packed_mem)
|
||||
void check_design(RTLIL::Design *design, bool &has_top, bool &has_sync_init)
|
||||
{
|
||||
has_sync_init = has_packed_mem = has_top = false;
|
||||
has_sync_init = has_top = false;
|
||||
|
||||
for (auto module : design->modules()) {
|
||||
if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl_blackbox)))
|
||||
|
|
@ -2768,20 +2847,15 @@ struct CxxrtlWorker {
|
|||
for (auto sync : proc.second->syncs)
|
||||
if (sync->type == RTLIL::STi)
|
||||
has_sync_init = true;
|
||||
|
||||
// The Mem constructor also checks for well-formedness of $meminit cells, if any.
|
||||
for (auto &mem : Mem::get_all_memories(module))
|
||||
if (mem.packed)
|
||||
has_packed_mem = true;
|
||||
}
|
||||
}
|
||||
|
||||
void prepare_design(RTLIL::Design *design)
|
||||
{
|
||||
bool did_anything = false;
|
||||
bool has_top, has_sync_init, has_packed_mem;
|
||||
bool has_top, has_sync_init;
|
||||
log_push();
|
||||
check_design(design, has_top, has_sync_init, has_packed_mem);
|
||||
check_design(design, has_top, has_sync_init);
|
||||
if (run_hierarchy && !has_top) {
|
||||
Pass::call(design, "hierarchy -auto-top");
|
||||
did_anything = true;
|
||||
|
|
@ -2801,14 +2875,10 @@ struct CxxrtlWorker {
|
|||
Pass::call(design, "proc_init");
|
||||
did_anything = true;
|
||||
}
|
||||
if (has_packed_mem) {
|
||||
Pass::call(design, "memory_unpack");
|
||||
did_anything = true;
|
||||
}
|
||||
// Recheck the design if it was modified.
|
||||
if (did_anything)
|
||||
check_design(design, has_top, has_sync_init, has_packed_mem);
|
||||
log_assert(!has_sync_init && !has_packed_mem);
|
||||
check_design(design, has_top, has_sync_init);
|
||||
log_assert(!has_sync_init);
|
||||
log_pop();
|
||||
if (did_anything)
|
||||
log_spacer();
|
||||
|
|
|
|||
Loading…
Reference in New Issue