riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Hotfix for 4c82ddf 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-21 19:27:23 +01:00
parent 3b97b612fe
commit d55790909c
1 changed files with 2 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
passes/cmds/setundef.cc
View File

@ -238,20 +238,11 @@ struct SetundefPass : public Pass {
{ {
if (params_mode) if (params_mode)
{ {
for (auto *cell : module->cells()) for (auto *cell : module->selected_cells()) {
{ for (auto &parameter : cell->parameters) {
// Only modify selected cells.
if (!design->selected(module, it)) {
continue;
}
for (auto &parameter : cell->parameters)
{
for (auto &bit : parameter.second.bits) { for (auto &bit : parameter.second.bits) {
if (bit > RTLIL::State::S1) if (bit > RTLIL::State::S1)
{
bit = worker.next_bit(); bit = worker.next_bit();
}
} }
} }
} }