riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Revert enable check

This commit is contained in:
Eddie Hung 2019-05-25 12:55:57 -07:00
parent f3e86e06e6
commit d4fb6cac7c
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/opt/opt_rmdff.cc
View File

@ -385,9 +385,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
// (ii) reset value is same as constant D // (ii) reset value is same as constant D
// and (a) has no initial value // and (a) has no initial value
// (b) initial value same as constant D // (b) initial value same as constant D
// and (1) has no enable signal if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
// (2) enable is always active
if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const()) && (!sig_e.size() || (sig_d.is_fully_undef() && !has_init))) {
// Q is permanently D // Q is permanently D
mod->connect(sig_q, sig_d); mod->connect(sig_q, sig_d);
goto delete_dff; goto delete_dff;