mirror of https://github.com/YosysHQ/yosys.git
Added support for sat -show @<sel_name>
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@ -733,6 +733,10 @@ struct SatPass : public Pass {
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log(" show the model for the specified signal. if no -show option is\n");
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log(" show the model for the specified signal. if no -show option is\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
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log("\n");
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log("\n");
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log(" -show @<sel_name>\n");
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log(" add all wires from the specified selection (see help select) to\n");
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log(" the list of signals to be shown.\n");
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log("\n");
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log(" -show-inputs, -show-outputs\n");
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log(" -show-inputs, -show-outputs\n");
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log(" add all module input (output) ports to the list of shown signals\n");
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log(" add all module input (output) ports to the list of shown signals\n");
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log("\n");
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log("\n");
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@ -1022,6 +1026,19 @@ struct SatPass : public Pass {
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sets_def.push_back(it.second->name);
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sets_def.push_back(it.second->name);
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}
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}
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for (auto &str : shows) {
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if (str.empty() || str[0] != '@')
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continue;
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str = RTLIL::escape_id(str.substr(1));
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if (design->selection_vars.count(str) == 0)
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log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str));
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RTLIL::Selection &sel = design->selection_vars.at(str);
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str.clear();
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for (auto &it : module->wires)
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if (sel.selected_member(module->name, it.first))
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str += (str.empty() ? "" : ",") + it.first;
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}
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if (show_inputs) {
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if (show_inputs) {
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for (auto &it : module->wires)
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for (auto &it : module->wires)
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if (it.second->port_input)
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if (it.second->port_input)
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