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Add #1598 testcase

This commit is contained in:
Eddie Hung 2019-12-27 16:44:57 -08:00
parent 237415e78c
commit d45869855c
3 changed files with 48 additions and 0 deletions
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16
tests/arch/ecp5/bug1598.ys Normal file
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read_verilog <<EOT
module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9

16
tests/arch/ice40/bug1598.ys Normal file
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read_verilog <<EOT
module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9

16
tests/arch/xilinx/bug1598.ys Normal file
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@ -0,0 +1,16 @@
read_verilog <<EOT
module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9