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Use read_args for read_verilog

This commit is contained in:
Eddie Hung 2019-10-04 17:27:05 -07:00
parent 7959e9d6b2
commit d4212d128b
1 changed files with 6 additions and 3 deletions
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9
techlibs/xilinx/synth_xilinx.cc
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@ -283,10 +283,13 @@ struct SynthXilinxPass : public ScriptPass
ff_map_file = "+/xilinx/xc7_ff_map.v";
if (check_label("begin")) {
std::string read_args;
if (vpr)
run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
read_args += " -D_EXPLICIT_CARRY";
if (abc9)
read_args += " -D_ABC9";
read_args += " -lib +/xilinx/cells_sim.v";
run("read_verilog" + read_args);
if (help_mode)
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");