From d41688f7d72c446c3dc158f52568317e2a56ed4b Mon Sep 17 00:00:00 2001 From: Tony Min <170435972+tony-min-1@users.noreply.github.com> Date: Mon, 8 Jul 2024 10:57:16 -0400 Subject: [PATCH] Revisions (#4) * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony --- passes/pmgen/microchip_dsp.pmg | 6 +- passes/pmgen/microchip_dsp_CREG.pmg | 2 +- techlibs/microchip/cells_sim.v | 150 +----------------- techlibs/microchip/microchip_dffopt.cc | 3 + techlibs/microchip/synth_microchip.cc | 53 ++++--- tests/arch/microchip/Registers.v | 38 ----- tests/arch/microchip/Registers.ys | 24 --- tests/arch/microchip/carryout.v | 34 ---- tests/arch/microchip/carryout.ys | 22 --- tests/arch/microchip/cascade.v | 38 ----- tests/arch/microchip/cascade.ys | 22 --- tests/arch/microchip/dff.ys | 76 +++++++++ tests/arch/microchip/dff_opt.ys | 2 +- tests/arch/microchip/dsp.ys | 211 +++++++++++++++++++++++++ tests/arch/microchip/full_dsp.v | 30 ---- tests/arch/microchip/full_dsp.ys | 22 --- tests/arch/microchip/large_mult.v | 25 --- tests/arch/microchip/large_mult.ys | 23 --- tests/arch/microchip/mac.v | 43 ----- tests/arch/microchip/mac.ys | 24 --- tests/arch/microchip/mult.ys | 51 ++++++ tests/arch/microchip/postAdd_mult.v | 30 ---- tests/arch/microchip/postAdd_mult.ys | 22 --- tests/arch/microchip/post_adder.v | 32 ---- tests/arch/microchip/post_adder.ys | 23 --- tests/arch/microchip/pre_adder_dsp.v | 30 ---- tests/arch/microchip/pre_adder_dsp.ys | 22 --- tests/arch/microchip/ram_SDP.ys | 12 +- tests/arch/microchip/ram_TDP.v | 36 ++--- tests/arch/microchip/ram_TDP.ys | 14 +- tests/arch/microchip/reduce.ys | 2 +- tests/arch/microchip/reg_c.v | 122 -------------- tests/arch/microchip/reg_c.ys | 22 --- tests/arch/microchip/reg_test.v | 97 ------------ tests/arch/microchip/reg_test.ys | 22 --- tests/arch/microchip/signed_mult.v | 28 ---- tests/arch/microchip/signed_mult.ys | 22 --- tests/arch/microchip/simple_ram.v | 37 ----- tests/arch/microchip/simple_ram.ys | 10 +- tests/arch/microchip/unsigned_mult.v | 28 ---- tests/arch/microchip/unsigned_mult.ys | 22 --- tests/arch/microchip/uram_ar.ys | 2 +- tests/arch/microchip/uram_sr.ys | 2 +- tests/arch/microchip/widemux.ys | 17 +- 44 files changed, 435 insertions(+), 1118 deletions(-) delete mode 100644 tests/arch/microchip/Registers.v delete mode 100644 tests/arch/microchip/Registers.ys delete mode 100644 tests/arch/microchip/carryout.v delete mode 100644 tests/arch/microchip/carryout.ys delete mode 100644 tests/arch/microchip/cascade.v delete mode 100644 tests/arch/microchip/cascade.ys create mode 100644 tests/arch/microchip/dff.ys create mode 100644 tests/arch/microchip/dsp.ys delete mode 100644 tests/arch/microchip/full_dsp.v delete mode 100644 tests/arch/microchip/full_dsp.ys delete mode 100644 tests/arch/microchip/large_mult.v delete mode 100644 tests/arch/microchip/large_mult.ys delete mode 100644 tests/arch/microchip/mac.v delete mode 100644 tests/arch/microchip/mac.ys create mode 100644 tests/arch/microchip/mult.ys delete mode 100644 tests/arch/microchip/postAdd_mult.v delete mode 100644 tests/arch/microchip/postAdd_mult.ys delete mode 100644 tests/arch/microchip/post_adder.v delete mode 100644 tests/arch/microchip/post_adder.ys delete mode 100644 tests/arch/microchip/pre_adder_dsp.v delete mode 100644 tests/arch/microchip/pre_adder_dsp.ys delete mode 100644 tests/arch/microchip/reg_c.v delete mode 100644 tests/arch/microchip/reg_c.ys delete mode 100644 tests/arch/microchip/reg_test.v delete mode 100644 tests/arch/microchip/reg_test.ys delete mode 100755 tests/arch/microchip/signed_mult.v delete mode 100755 tests/arch/microchip/signed_mult.ys delete mode 100644 tests/arch/microchip/simple_ram.v delete mode 100644 tests/arch/microchip/unsigned_mult.v delete mode 100644 tests/arch/microchip/unsigned_mult.ys diff --git a/passes/pmgen/microchip_dsp.pmg b/passes/pmgen/microchip_dsp.pmg index 1c22bb317..9a6b9e1fa 100644 --- a/passes/pmgen/microchip_dsp.pmg +++ b/passes/pmgen/microchip_dsp.pmg @@ -126,7 +126,7 @@ code sigA sigB sigD preAdderStatic moveBtoA // sigA should be the input to the multiplier without the preAdd. sigB and sigD should be //the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then // we basically swap it. - sigA = port(dsp, \B); + sigA = sigB; } // port B of preAdderStatic must be mapped to port D of DSP for subtraction @@ -368,7 +368,7 @@ match ff filter !ff->type.in($adff, $adffe) || allowAsync // clock must be consistent - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ @@ -415,7 +415,7 @@ match ff filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter port(ff, \D).extract(offset, GetSize(argD)) == argD - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/passes/pmgen/microchip_dsp_CREG.pmg b/passes/pmgen/microchip_dsp_CREG.pmg index baa586962..d1b15d460 100644 --- a/passes/pmgen/microchip_dsp_CREG.pmg +++ b/passes/pmgen/microchip_dsp_CREG.pmg @@ -145,7 +145,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v index eb06a0e69..de4e3607f 100644 --- a/techlibs/microchip/cells_sim.v +++ b/techlibs/microchip/cells_sim.v @@ -51,7 +51,7 @@ module CFG1 ( endspecify endmodule -(* abc9_lut=2 *) +(* abc9_lut=1 *) module CFG2 ( output Y, input A, @@ -65,7 +65,7 @@ module CFG2 ( endspecify endmodule -(* abc9_lut=3 *) +(* abc9_lut=1 *) module CFG3 ( output Y, input A, @@ -81,7 +81,7 @@ module CFG3 ( endspecify endmodule -(* abc9_lut=3 *) +(* abc9_lut=1 *) module CFG4 ( output Y, input A, @@ -291,13 +291,6 @@ module ARI1 ( endspecify endmodule -// module FCEND_BUFF -// module FCINIT_BUFF -// module FLASH_FREEZE -// module OSCILLATOR -// module SYSCTRL_RESET_STATUS -// module LIVE_PROBE_FB - (* blackbox *) module GCLKBUF ( (* iopad_external_pin *) @@ -320,28 +313,6 @@ module GCLKBUF_DIFF ( ); endmodule -(* blackbox *) -module GCLKBIBUF ( - input D, - input E, - input EN, - (* iopad_external_pin *) - inout PAD, - (* clkbuf_driver *) - output Y -); -endmodule - -// module DFN1 -// module DFN1C0 -// module DFN1E1 -// module DFN1E1C0 -// module DFN1E1P0 -// module DFN1P0 -// module DLN1 -// module DLN1C0 -// module DLN1P0 - module INV ( input A, output Y @@ -588,121 +559,6 @@ module TRIBUFF_DIFF ( parameter IOSTD = ""; endmodule -// module DDR_IN -// module DDR_OUT -// module RAM1K18 -// module RAM64x18 -// module MACC - -(* blackbox *) -module SYSRESET ( - (* iopad_external_pin *) - input DEVRST_N, - output POWER_ON_RESET_N); -endmodule - - -(* blackbox *) -module XTLOSC ( - (* iopad_external_pin *) - input XTL, - output CLKOUT); - parameter [1:0] MODE = 2'h3; - parameter real FREQUENCY = 20.0; -endmodule - -(* blackbox *) -module RAM1K18 ( - input [13:0] A_ADDR, - input [2:0] A_BLK, - (* clkbuf_sink *) - input A_CLK, - input [17:0] A_DIN, - output [17:0] A_DOUT, - input [1:0] A_WEN, - input [2:0] A_WIDTH, - input A_WMODE, - input A_ARST_N, - input A_DOUT_LAT, - input A_DOUT_ARST_N, - (* clkbuf_sink *) - input A_DOUT_CLK, - input A_DOUT_EN, - input A_DOUT_SRST_N, - - input [13:0] B_ADDR, - input [2:0] B_BLK, - (* clkbuf_sink *) - input B_CLK, - input [17:0] B_DIN, - output [17:0] B_DOUT, - input [1:0] B_WEN, - input [2:0] B_WIDTH, - input B_WMODE, - input B_ARST_N, - input B_DOUT_LAT, - input B_DOUT_ARST_N, - (* clkbuf_sink *) - input B_DOUT_CLK, - input B_DOUT_EN, - input B_DOUT_SRST_N, - input A_EN, - input B_EN, - input SII_LOCK, - output BUSY); -endmodule - -(* blackbox *) -module RAM64x18 ( - input [9:0] A_ADDR, - input [1:0] A_BLK, - input [2:0] A_WIDTH, - output [17:0] A_DOUT, - input A_DOUT_ARST_N, - (* clkbuf_sink *) - input A_DOUT_CLK, - input A_DOUT_EN, - input A_DOUT_LAT, - input A_DOUT_SRST_N, - (* clkbuf_sink *) - input A_ADDR_CLK, - input A_ADDR_EN, - input A_ADDR_LAT, - input A_ADDR_SRST_N, - input A_ADDR_ARST_N, - - input [9:0] B_ADDR, - input [1:0] B_BLK, - input [2:0] B_WIDTH, - output [17:0] B_DOUT, - input B_DOUT_ARST_N, - (* clkbuf_sink *) - input B_DOUT_CLK, - input B_DOUT_EN, - input B_DOUT_LAT, - input B_DOUT_SRST_N, - (* clkbuf_sink *) - input B_ADDR_CLK, - input B_ADDR_EN, - input B_ADDR_LAT, - input B_ADDR_SRST_N, - input B_ADDR_ARST_N, - - input [9:0] C_ADDR, - (* clkbuf_sink *) - input C_CLK, - input [17:0] C_DIN, - input C_WEN, - input [1:0] C_BLK, - input [2:0] C_WIDTH, - - input A_EN, - input B_EN, - input C_EN, - input SII_LOCK, - output BUSY); -endmodule - (* blackbox *) module MACC_PA ( input DOTP, diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index 4193eb469..62450ab6e 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -218,6 +218,7 @@ struct MicrochipDffOptPass : public Pass { worthy_post_ce = true; } else if (sig_CE.data != State::S1) { // Strange. Should not happen in a reasonable flow, so bail. + log_assert(false); // This DFF is always off continue; } else { lut_d_post_ce = lut_d; @@ -241,6 +242,7 @@ struct MicrochipDffOptPass : public Pass { worthy_post_s = true; } else if (sig_S.data != (inv_s ? State::S1 : State::S0)) { // Strange. Should not happen in a reasonable flow, so bail. + log_assert(false); // DFF is always in set mode continue; } } @@ -263,6 +265,7 @@ struct MicrochipDffOptPass : public Pass { worthy_post_r = true; } else if (sig_R.data != (inv_r ? State::S1 : State::S0)) { // Strange. Should not happen in a reasonable flow, so bail. + log_assert(false); // DFF is always in reset mode continue; } } diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc index 9b7adae1b..2da4c4000 100644 --- a/techlibs/microchip/synth_microchip.cc +++ b/techlibs/microchip/synth_microchip.cc @@ -33,10 +33,8 @@ struct SynthMicrochipPass : public ScriptPass { log("\n"); log(" synth_microchip [options]\n"); log("\n"); - log("This command runs synthesis for Microchip FPGAs. Operating on\n"); - log("partly selected designs is not supported (you must submit a fully-selected \n"); - log("design). This command creates netlists that are compatible with Microchip \n"); - log("PolarFire devices.\n"); + log("This command runs synthesis for Microchip FPGAs. This command creates \n"); + log("netlists that are compatible with Microchip PolarFire devices. \n"); log("\n"); log(" -top \n"); log(" use the specified module as the top module\n"); @@ -55,6 +53,9 @@ struct SynthMicrochipPass : public ScriptPass { log(" Write the design to the specified BLIF file. Writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); + log(" -vlog \n"); + log(" write the design to the specified Verilog file. writing of an output\n"); + log(" file is omitted if this parameter is not specified.\n"); log(" -nobram\n"); log(" Do not use block RAM cells in output netlist\n"); log("\n"); @@ -76,11 +77,8 @@ struct SynthMicrochipPass : public ScriptPass { log(" 'from_label' is synonymous to 'begin', and empty 'to_label' is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -flatten\n"); - log(" Flatten design before synthesis.\n"); - log("\n"); - log(" -flatten_before_abc\n"); - log(" Flatten design before abc tech mapping.\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); log("\n"); log(" -dff\n"); log(" Run 'abc'/'abc9' with -dff option\n"); @@ -89,8 +87,8 @@ struct SynthMicrochipPass : public ScriptPass { log(" Run 'abc' with '-D 1' option to enable flip-flop retiming.\n"); log(" implies -dff.\n"); log("\n"); - log(" -abc9\n"); - log(" Use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -abc\n"); + log(" Use classic ABC flow instead of ABC9\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -98,10 +96,9 @@ struct SynthMicrochipPass : public ScriptPass { log("\n"); } - std::string top_opt, edif_file, blif_file, family; + std::string top_opt, edif_file, blif_file, vlog_file, family; bool flatten, retime, noiopad, noclkbuf, nobram, nocarry, nowidelut, nodsp; bool abc9, dff; - bool flatten_before_abc; int lut_size; // debug dump switches @@ -112,8 +109,9 @@ struct SynthMicrochipPass : public ScriptPass { top_opt = "-auto-top"; edif_file.clear(); blif_file.clear(); + vlog_file.clear(); family = "polarfire"; - flatten = false; + flatten = true; retime = false; noiopad = false; noclkbuf = false; @@ -121,9 +119,8 @@ struct SynthMicrochipPass : public ScriptPass { nobram = false; nowidelut = false; nodsp = false; - abc9 = false; + abc9 = true; dff = false; - flatten_before_abc = false; lut_size = 4; debug_memory = false; @@ -153,6 +150,10 @@ struct SynthMicrochipPass : public ScriptPass { blif_file = args[++argidx]; continue; } + if (args[argidx] == "-vlog" && argidx + 1 < args.size()) { + vlog_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx + 1 < args.size()) { size_t pos = args[argidx + 1].find(':'); if (pos == std::string::npos) @@ -161,12 +162,8 @@ struct SynthMicrochipPass : public ScriptPass { run_to = args[argidx].substr(pos + 1); continue; } - if (args[argidx] == "-flatten") { - flatten = true; - continue; - } - if (args[argidx] == "-flatten_before_abc") { - flatten_before_abc = true; + if (args[argidx] == "-noflatten") { + flatten = false; continue; } if (args[argidx] == "-retime") { @@ -201,8 +198,8 @@ struct SynthMicrochipPass : public ScriptPass { nobram = true; continue; } - if (args[argidx] == "-abc9") { - abc9 = true; + if (args[argidx] == "-abc") { + abc9 = false; continue; } if (args[argidx] == "-nodsp") { @@ -479,8 +476,6 @@ struct SynthMicrochipPass : public ScriptPass { if (check_label("map_luts")) { run("opt_expr -mux_undef -noclkinv"); - if (flatten_before_abc) - run("flatten"); if (help_mode) run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); else if (abc9) { @@ -535,6 +530,12 @@ struct SynthMicrochipPass : public ScriptPass { if (!blif_file.empty() || help_mode) run(stringf("write_blif %s", blif_file.c_str())); } + + if (check_label("vlog")) + { + if (!vlog_file.empty() || help_mode) + run(stringf("write_verilog %s", help_mode ? "" : vlog_file.c_str())); + } } } SynthMicrochipPass; diff --git a/tests/arch/microchip/Registers.v b/tests/arch/microchip/Registers.v deleted file mode 100644 index 160c09cc7..000000000 --- a/tests/arch/microchip/Registers.v +++ /dev/null @@ -1,38 +0,0 @@ -/* -ISC License - -Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries - -Permission to use, copy, modify, and/or distribute this software for any -purpose with or without fee is hereby granted, provided that the above -copyright notice and this permission notice appear in all copies. - -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - -module Registers( - input clk, - input en, - input rst, - input D, - output reg Q -); -parameter LOAD_DATA = 1; - -// active low async reset -always @(posedge clk, negedge rst) begin - if (rst == 0) begin - Q <= LOAD_DATA; - end else if(en) begin - Q <= D; - end -end - - -endmodule \ No newline at end of file diff --git a/tests/arch/microchip/Registers.ys b/tests/arch/microchip/Registers.ys deleted file mode 100644 index bbf7a6c91..000000000 --- a/tests/arch/microchip/Registers.ys +++ /dev/null @@ -1,24 +0,0 @@ -# ISC License -# -# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -# read verilog files -read_verilog Registers.v - -synth_microchip -top Registers -abc9 -family polarfire -noiopad - -select -assert-count 1 t:SLE -select -assert-count 1 t:CLKBUF -select -assert-none t:SLE t:CLKBUF %% t:* %D diff --git a/tests/arch/microchip/carryout.v b/tests/arch/microchip/carryout.v deleted file mode 100644 index 8da139774..000000000 --- a/tests/arch/microchip/carryout.v +++ /dev/null @@ -1,34 +0,0 @@ -/* -ISC License - -Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries - -Permission to use, copy, modify, and/or distribute this software for any -purpose with or without fee is hereby granted, provided that the above -copyright notice and this permission notice appear in all copies. - -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - -module carryout (cout,out,a, b,c); -parameter n = 6; -parameter k = 2; -output reg [k*(n+1)-1:0] out; -output reg cout; -input [n:0] a; -input [n:0] b; -input [n-1:0] c; - - always @(a,b,c) - begin - {cout,out} = a * b + c; - - end - -endmodule diff --git a/tests/arch/microchip/carryout.ys b/tests/arch/microchip/carryout.ys deleted file mode 100644 index 7c79dfba3..000000000 --- a/tests/arch/microchip/carryout.ys +++ /dev/null @@ -1,22 +0,0 @@ -# ISC License -# -# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -read_verilog carryout.v - -synth_microchip -top carryout -abc9 -family polarfire -noiopad - -select -assert-count 1 t:MACC_PA -select -assert-none t:MACC_PA %% t:* %D diff --git a/tests/arch/microchip/cascade.v b/tests/arch/microchip/cascade.v deleted file mode 100644 index 19dbac9dd..000000000 --- a/tests/arch/microchip/cascade.v +++ /dev/null @@ -1,38 +0,0 @@ -/* -ISC License - -Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries - -Permission to use, copy, modify, and/or distribute this software for any -purpose with or without fee is hereby granted, provided that the above -copyright notice and this permission notice appear in all copies. - -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - -module cascade( - input signed [5:0] in_A, - input signed [4:0] in_B, - input signed [4:0] in_D, - output signed [11:0] out_P, - - input signed [4:0] casA, - input signed [4:0] casB - -); - -wire signed [9:0] cascade; -// first dsp -assign cascade = casA * casB; - -// second dsp -assign out_P = in_A * (in_B + in_D) + cascade; - - -endmodule diff --git a/tests/arch/microchip/cascade.ys b/tests/arch/microchip/cascade.ys deleted file mode 100644 index 7248c5625..000000000 --- a/tests/arch/microchip/cascade.ys +++ /dev/null @@ -1,22 +0,0 @@ -# ISC License -# -# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -read_verilog cascade.v - -synth_microchip -top cascade -abc9 -family polarfire -noiopad - -select -assert-count 2 t:MACC_PA -select -assert-none t:MACC_PA %% t:* %D diff --git a/tests/arch/microchip/dff.ys b/tests/arch/microchip/dff.ys new file mode 100644 index 000000000..ee377bb40 --- /dev/null +++ b/tests/arch/microchip/dff.ys @@ -0,0 +1,76 @@ +# ISC License +# +# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + + +# active low async reset with enable +read_verilog <