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flatten: simplify. NFC. 

Remove redundant sigmaps.
This commit is contained in:
whitequark 2020-06-03 16:25:46 +00:00
parent 66255dab4e
commit d3e2100306
1 changed files with 3 additions and 7 deletions
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10
passes/techmap/flatten.cc
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@ -52,7 +52,6 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
struct FlattenWorker struct FlattenWorker
{ {
dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> cache; dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> cache;
dict<Module*, SigMap> sigmaps;
pool<IdString> flatten_do_list; pool<IdString> flatten_do_list;
pool<IdString> flatten_done_list; pool<IdString> flatten_done_list;
@ -122,6 +121,8 @@ struct FlattenWorker
design->select(module, w); design->select(module, w);
} }
SigMap sigmap(module);
SigMap tpl_sigmap(tpl); SigMap tpl_sigmap(tpl);
pool<SigBit> tpl_written_bits; pool<SigBit> tpl_written_bits;
@ -185,10 +186,7 @@ struct FlattenWorker
// connect internal and external wires // connect internal and external wires
if (sigmaps.count(module) == 0) if (sigmap(c.first).has_const())
sigmaps[module].set(module);
if (sigmaps.at(module)(c.first).has_const())
log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
@ -258,8 +256,6 @@ struct FlattenWorker
bool did_something = false; bool did_something = false;
LogMakeDebugHdl mkdebug; LogMakeDebugHdl mkdebug;
SigMap sigmap(module);
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (!design->has(cell->type)) if (!design->has(cell->type))