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Added recursion support to techmap

This commit is contained in:
Clifford Wolf 2014-02-16 17:16:44 +01:00
parent aeb36b0b8b
commit d3dc22a90f
1 changed files with 290 additions and 288 deletions
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26
passes/techmap/techmap.cc
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@ -50,6 +50,8 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
}
}
struct TechmapWorker
{
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
std::map<RTLIL::Module*, bool> techmap_do_cache;
@ -61,7 +63,7 @@ struct TechmapWireData {
typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
static TechmapWires techmap_find_special_wires(RTLIL::Module *module)
TechmapWires techmap_find_special_wires(RTLIL::Module *module)
{
TechmapWires result;
@ -96,7 +98,7 @@ static TechmapWires techmap_find_special_wires(RTLIL::Module *module)
return result;
}
static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
{
log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
@ -189,7 +191,7 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module,
delete cell;
}
static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
{
if (!design->selected(module))
@ -361,6 +363,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
return did_something;
}
};
struct TechmapPass : public Pass {
TechmapPass() : Pass("techmap", "generic technology mapper") { }
@ -469,7 +472,8 @@ struct TechmapPass : public Pass {
}
extra_args(args, argidx, design);
simplemap_get_mappers(simplemap_mappers);
TechmapWorker worker;
simplemap_get_mappers(worker.simplemap_mappers);
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
@ -509,17 +513,15 @@ struct TechmapPass : public Pass {
while (did_something) {
did_something = false;
for (auto &mod_it : design->modules)
if (techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
did_something = true;
if (did_something)
design->check();
}
log("No more expansions possible.\n");
techmap_cache.clear();
techmap_do_cache.clear();
simplemap_mappers.clear();
delete map;
log_pop();
}
} TechmapPass;
@ -544,6 +546,8 @@ struct FlattenPass : public Pass {
extra_args(args, 1, design);
TechmapWorker worker;
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
for (auto &it : design->modules)
celltypeMap[it.first].insert(it.first);
@ -559,11 +563,11 @@ struct FlattenPass : public Pass {
while (did_something) {
did_something = false;
if (top_mod != NULL) {
if (techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
did_something = true;
} else {
for (auto &mod_it : design->modules)
if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
did_something = true;
}
}
@ -582,8 +586,6 @@ struct FlattenPass : public Pass {
design->modules.swap(new_modules);
}
techmap_cache.clear();
techmap_do_cache.clear();
log_pop();
}
} FlattenPass;