mirror of https://github.com/YosysHQ/yosys.git
Fix muxcover and its techmapping
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@ -254,11 +254,11 @@ endmodule
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module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
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module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
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input A, B, C, D, E, F, G, H, S, T, U;
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input A, B, C, D, E, F, G, H, S, T, U;
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output Y;
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output Y;
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\$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y));
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\$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
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endmodule
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endmodule
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module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
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module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
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input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
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input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
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output Y;
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output Y;
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\$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y));
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\$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
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endmodule
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endmodule
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@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass
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if (check_label("map_cells")) {
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if (check_label("map_cells")) {
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if (!nomux || help_mode)
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if (!nomux || help_mode)
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run("muxcover", "(skip if '-nomux')");
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run("muxcover -mux8 -mux16", "(skip if '-nomux')");
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run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
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run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
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run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
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run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
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"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
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"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
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