mirror of https://github.com/YosysHQ/yosys.git
Cleanups and improvements in wreduce pass
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parent
1c182cedb7
commit
d3b1a29708
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@ -61,8 +61,10 @@ struct WreduceWorker
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WreduceWorker(WreduceConfig *config, Module *module) :
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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config(config), module(module), mi(module) { }
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void run_cell_mux(Cell *cell)
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bool run_cell_mux(Cell *cell)
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{
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{
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// Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused
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SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
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SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
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SigSpec sig_b = mi.sigmap(cell->getPort("\\B"));
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SigSpec sig_b = mi.sigmap(cell->getPort("\\B"));
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SigSpec sig_s = mi.sigmap(cell->getPort("\\S"));
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SigSpec sig_s = mi.sigmap(cell->getPort("\\S"));
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@ -90,49 +92,60 @@ struct WreduceWorker
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bits_removed.push_back(ref);
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bits_removed.push_back(ref);
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}
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}
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if (!bits_removed.empty())
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if (bits_removed.empty())
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{
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return false;
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SigSpec sig_removed;
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for (int i = SIZE(bits_removed)-1; i >= 0; i--)
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sig_removed.append_bit(bits_removed[i]);
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log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
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SigSpec sig_removed;
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SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type));
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for (int i = SIZE(bits_removed)-1; i >= 0; i--)
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sig_removed.append_bit(bits_removed[i]);
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int n_removed = SIZE(sig_removed);
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log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
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int n_kept = SIZE(sig_y) - SIZE(sig_removed);
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SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type));
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SigSpec new_work_queue_bits;
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int n_removed = SIZE(sig_removed);
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new_work_queue_bits.append(sig_a.extract(n_kept, n_removed));
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int n_kept = SIZE(sig_y) - SIZE(sig_removed);
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new_work_queue_bits.append(sig_y.extract(n_kept, n_removed));
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SigSpec new_sig_a = sig_a.extract(0, n_kept);
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SigSpec new_work_queue_bits;
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SigSpec new_sig_y = sig_y.extract(0, n_kept);
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new_work_queue_bits.append(sig_a.extract(n_kept, n_removed));
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SigSpec new_sig_b;
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new_work_queue_bits.append(sig_y.extract(n_kept, n_removed));
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for (int k = 0; k < SIZE(sig_s); k++) {
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SigSpec new_sig_a = sig_a.extract(0, n_kept);
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new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept));
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SigSpec new_sig_y = sig_y.extract(0, n_kept);
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new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed));
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SigSpec new_sig_b;
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}
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for (auto bit : new_work_queue_bits)
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for (int k = 0; k < SIZE(sig_s); k++) {
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work_queue_bits.insert(bit);
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new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept));
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new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed));
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cell->setPort("\\A", new_sig_a);
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cell->setPort("\\B", new_sig_b);
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cell->setPort("\\Y", new_sig_y);
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cell->fixup_parameters();
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module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
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}
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}
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for (auto bit : new_work_queue_bits)
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work_queue_bits.insert(bit);
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cell->setPort("\\A", new_sig_a);
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cell->setPort("\\B", new_sig_b);
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cell->setPort("\\Y", new_sig_y);
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cell->fixup_parameters();
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module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
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return true;
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}
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}
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void run_reduce_inport(Cell *cell, char port)
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bool run_reduce_inport(Cell *cell, char port, int max_port_size)
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{
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{
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bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
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bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
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SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
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SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
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if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
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is_signed = false;
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int bits_removed = 0;
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int bits_removed = 0;
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if (SIZE(sig) > max_port_size) {
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bits_removed = SIZE(sig) - max_port_size;
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for (auto bit : sig.extract(max_port_size, bits_removed))
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work_queue_bits.insert(bit);
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sig = sig.extract(0, max_port_size);
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}
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if (is_signed) {
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if (is_signed) {
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while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == constmap(sig[SIZE(sig)-2]))
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while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == constmap(sig[SIZE(sig)-2]))
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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@ -141,31 +154,44 @@ struct WreduceWorker
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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}
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}
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if (bits_removed) {
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if (bits_removed == 0)
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log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
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return false;
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bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort(stringf("\\%c", port), sig);
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log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
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}
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bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort(stringf("\\%c", port), sig);
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return true;
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}
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}
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void run_cell(Cell *cell)
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bool run_cell(Cell *cell)
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{
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{
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if (!cell->type.in(config->supported_cell_types))
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bool did_something = false;
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return;
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if (cell->type.in("$mux", "$pmux", "$safe_pmux")) {
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if (!cell->type.in(config->supported_cell_types))
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run_cell_mux(cell);
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return false;
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return;
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if (cell->type.in("$mux", "$pmux", "$safe_pmux"))
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return run_cell_mux(cell);
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// Reduce size of ports A and B based on constant input bits and size of output port
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int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1;
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int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1;
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if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
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max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y")));
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max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y")));
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}
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}
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if (cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
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if (max_port_a_size >= 0)
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cell->setParam("\\B_SIGNED", false);
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did_something = run_reduce_inport(cell, 'A', max_port_a_size) || did_something;
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if (cell->hasParam("\\A_SIGNED"))
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if (max_port_b_size >= 0)
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run_reduce_inport(cell, 'A');
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did_something = run_reduce_inport(cell, 'B', max_port_b_size) || did_something;
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if (cell->hasParam("\\B_SIGNED"))
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run_reduce_inport(cell, 'B');
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// Reduce size of port Y based on sizes for A and B and unused bits in Y
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SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
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SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
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@ -208,9 +234,13 @@ struct WreduceWorker
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log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
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log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
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bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
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bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort("\\Y", sig);
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cell->setPort("\\Y", sig);
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did_something = true;
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}
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}
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cell->fixup_parameters();
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if (did_something)
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cell->fixup_parameters();
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return did_something;
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}
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}
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void run()
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void run()
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@ -222,7 +252,7 @@ struct WreduceWorker
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{
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{
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work_queue_bits.clear();
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work_queue_bits.clear();
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for (auto c : work_queue_cells)
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for (auto c : work_queue_cells)
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run_cell(c);
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while (run_cell(c)) { }
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work_queue_cells.clear();
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work_queue_cells.clear();
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for (auto bit : work_queue_bits)
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for (auto bit : work_queue_bits)
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