riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix tests 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-21 11:40:20 +02:00
parent 5b7fea5245
commit d38f0c1a96
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tests/tools/autotest.sh
View File

@ -7,7 +7,7 @@ use_modelsim=false
verbose=false verbose=false
keeprunning=false keeprunning=false
makejmode=false makejmode=false
frontend="verilog" frontend="verilog -noblackbox"
backend_opts="-noattr -noexpr -siminit" backend_opts="-noattr -noexpr -siminit"
autotb_opts="" autotb_opts=""
include_opts="" include_opts=""
@ -137,7 +137,7 @@ do
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
else else
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
frontend="verilog" frontend="verilog -noblackbox"
fi fi
if [ ! -f ../${bn}_tb.v ]; then if [ ! -f ../${bn}_tb.v ]; then

1
tests/various/hierarchy.sh
View File

@ -53,6 +53,7 @@ echo -n " no explicit top - "
module noTop(a, y); module noTop(a, y);
input a; input a;
output [31:0] y; output [31:0] y;
assign y = a;
endmodule endmodule
EOV EOV
hierarchy -auto-top hierarchy -auto-top