mirror of https://github.com/YosysHQ/yosys.git
More intuitive handling of "cd .." for singleton modules
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@ -1482,20 +1482,56 @@ struct CdPass : public Pass {
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log("\n");
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log(" cd ..\n");
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log("\n");
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log("Remove trailing substrings that start with '.' in current module name until\n");
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log("the name of a module in the current design is generated, then switch to that\n");
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log("module. Otherwise clear the current selection.\n");
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log("\n");
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log(" cd\n");
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log("\n");
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log("This is just a shortcut for 'select -clear'.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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if (args.size() != 2)
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if (args.size() != 1 && args.size() != 2)
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log_cmd_error("Invalid number of arguments.\n");
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if (args[1] == "..") {
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if (args.size() == 1 || args[1] == "/") {
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design->selection_stack.back() = RTLIL::Selection(true);
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design->selected_active_module = std::string();
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return;
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}
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if (args[1] == "..")
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{
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string modname = design->selected_active_module;
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design->selection_stack.back() = RTLIL::Selection(true);
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design->selected_active_module = std::string();
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while (1)
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{
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size_t pos = modname.rfind('.');
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if (pos == string::npos)
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break;
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modname = modname.substr(0, pos);
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Module *mod = design->module(modname);
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if (mod == nullptr)
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continue;
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design->selected_active_module = modname;
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design->selection_stack.back() = RTLIL::Selection();
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select_filter_active_mod(design, design->selection_stack.back());
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design->selection_stack.back().optimize(design);
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return;
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}
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return;
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}
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std::string modname = RTLIL::escape_id(args[1]);
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if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) {
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