From d2a04cca0e422ad73efe7364b395db07e7eedd28 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Thu, 25 Jan 2024 17:00:05 +0000 Subject: [PATCH] write_verilog: Making sure BUF cells are converted to expressions. These were previously not being converted correctly leading to yosys internal cells being written to my netlist. Signed-off-by: Ethan Mahintorabi --- backends/verilog/verilog_backend.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 47f1c4c2b..8febf0a96 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1053,6 +1053,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(";\n"); return true; } + + if (cell->type == ID($_BUF_)) { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::Y)); + f << stringf(" = "); + dump_attributes(f, "", cell->attributes, ' '); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(";\n"); + return true; + } if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { f << stringf("%s" "assign ", indent.c_str());