mirror of https://github.com/YosysHQ/yosys.git
Refactor common parts of SAT-using optimizations into a helper.
This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
This commit is contained in:
Marcelina Kościelnicka
parent
d8fcf1ab25
commit
d25b9088c8
3
Makefile
3
Makefile
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@ -575,6 +575,7 @@ $(eval $(call add_include_file,kernel/modtools.h))
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$(eval $(call add_include_file,kernel/macc.h))
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$(eval $(call add_include_file,kernel/utils.h))
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$(eval $(call add_include_file,kernel/satgen.h))
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$(eval $(call add_include_file,kernel/qcsat.h))
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$(eval $(call add_include_file,kernel/ff.h))
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$(eval $(call add_include_file,kernel/ffinit.h))
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$(eval $(call add_include_file,kernel/mem.h))
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@ -599,7 +600,7 @@ ifneq ($(ABCEXTERNAL),)
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kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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endif
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endif
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OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/mem.o kernel/ffmerge.o
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OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o
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kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"'
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kernel/yosys.o: CXXFLAGS += -DYOSYS_DATDIR='"$(DATDIR)"' -DYOSYS_PROGRAM_PREFIX='"$(PROGRAM_PREFIX)"'
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@ -380,9 +380,11 @@ struct ModWalker
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}
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}
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ModWalker(RTLIL::Design *design) : design(design), module(NULL)
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ModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)
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{
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ct.setup(design);
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if (module)
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setup(module);
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}
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void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)
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@ -0,0 +1,102 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/qcsat.h"
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USING_YOSYS_NAMESPACE
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std::vector<int> QuickConeSat::importSig(SigSpec sig)
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{
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sig = modwalker.sigmap(sig);
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for (auto bit : sig)
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bits_queue.insert(bit);
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return satgen.importSigSpec(sig);
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}
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int QuickConeSat::importSigBit(SigBit bit)
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{
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bit = modwalker.sigmap(bit);
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bits_queue.insert(bit);
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return satgen.importSigBit(bit);
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}
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void QuickConeSat::prepare()
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{
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while (!bits_queue.empty())
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{
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot) && !imported_onehot.count(bit.wire))
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{
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std::vector<int> bits = satgen.importSigSpec(bit.wire);
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for (int i : bits)
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for (int j : bits)
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if (i != j)
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ez->assume(ez->NOT(i), j);
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imported_onehot.insert(bit.wire);
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}
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bits_queue.clear();
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for (auto &pbit : portbits)
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{
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if (imported_cells.count(pbit.cell))
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continue;
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if (cell_complexity(pbit.cell) > max_cell_complexity)
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continue;
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if (max_cell_outs && GetSize(modwalker.cell_outputs[pbit.cell]) > max_cell_outs)
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continue;
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auto &inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(inputs.begin(), inputs.end());
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satgen.importCell(pbit.cell);
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imported_cells.insert(pbit.cell);
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}
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if (max_cell_count && GetSize(imported_cells) > max_cell_count)
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break;
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}
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}
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int QuickConeSat::cell_complexity(RTLIL::Cell *cell)
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{
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if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($_BUF_)))
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return 0;
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if (cell->type.in(ID($not), ID($and), ID($or), ID($xor), ID($xnor),
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ID($reduce_and), ID($reduce_or), ID($reduce_xor),
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ID($reduce_xnor), ID($reduce_bool),
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ID($logic_not), ID($logic_and), ID($logic_or),
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ID($eq), ID($ne), ID($eqx), ID($nex), ID($fa),
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ID($mux), ID($pmux), ID($lut), ID($sop),
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ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
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ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
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ID($_MUX_), ID($_NMUX_), ID($_MUX4_), ID($_MUX8_), ID($_MUX16_),
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ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
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return 1;
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if (cell->type.in(ID($neg), ID($add), ID($sub), ID($alu), ID($lcu),
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ID($lt), ID($le), ID($gt), ID($ge)))
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return 2;
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
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return 3;
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if (cell->type.in(ID($mul), ID($macc), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
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return 4;
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// Unknown cell.
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return 5;
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}
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@ -0,0 +1,76 @@
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/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef QCSAT_H
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#define QCSAT_H
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#include "kernel/satgen.h"
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#include "kernel/modtools.h"
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YOSYS_NAMESPACE_BEGIN
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// This is a helper class meant for easy construction of quick SAT queries
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// to a combinatorial input cone of some set of signals, meant for SAT-based
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// optimizations. Various knobs are provided to set just how much of the
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// cone should be included in the model — since this class is meant for
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// optimization, it should not be a correctness problem when some cells are
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// skipped and the solver spuriously returns SAT with a solution that
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// cannot exist in reality due to skipped constraints (ie. only UNSAT results
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// from this class should be considered binding).
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struct QuickConeSat {
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ModWalker &modwalker;
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ezSatPtr ez;
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SatGen satgen;
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// The effort level knobs.
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// The maximum "complexity level" of cells that will be imported.
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// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa
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// - 2: addition, subtraction, greater/less than comparisons, lcu
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// - 3: shifts
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// - 4: multiplication, division, power
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int max_cell_complexity = 2;
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// The maximum number of cells to import, or 0 for no limit.
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int max_cell_count = 0;
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// If non-0, skip importing cells with more than this number of output bits.
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int max_cell_outs = 0;
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// Internal state.
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pool<RTLIL::Cell*> imported_cells;
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pool<RTLIL::Wire*> imported_onehot;
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pool<RTLIL::SigBit> bits_queue;
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QuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}
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// Imports a signal into the SAT solver, queues its input cone to be
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// imported in the next prepare() call.
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std::vector<int> importSig(SigSpec sig);
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int importSigBit(SigBit bit);
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// Imports the input cones of all previously importSig'd signals into
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// the SAT solver.
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void prepare();
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// Returns the "complexity level" of a given cell.
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static int cell_complexity(RTLIL::Cell *cell);
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};
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YOSYS_NAMESPACE_END
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#endif
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@ -18,7 +18,7 @@
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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#include "kernel/qcsat.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/mem.h"
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@ -32,7 +32,6 @@ struct MemoryShareWorker
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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CellTypes cone_ct;
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bool flag_widen;
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@ -358,56 +357,20 @@ struct MemoryShareWorker
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// Okay, time to actually run the SAT solver.
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ezSatPtr ez;
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SatGen satgen(ez.get(), &modwalker.sigmap);
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QuickConeSat qcsat(modwalker);
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// create SAT representation of common input cone of all considered EN signals
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pool<Wire*> one_hot_wires;
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std::set<RTLIL::Cell*> sat_cells;
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std::set<RTLIL::SigBit> bits_queue;
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dict<int, int> port_to_sat_variable;
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for (auto idx : group) {
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RTLIL::SigSpec sig = modwalker.sigmap(mem.wr_ports[idx].en);
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port_to_sat_variable[idx] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
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for (auto idx : group)
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port_to_sat_variable[idx] = qcsat.ez->expression(qcsat.ez->OpOr, qcsat.importSig(mem.wr_ports[idx].en));
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std::vector<RTLIL::SigBit> bits = sig;
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bits_queue.insert(bits.begin(), bits.end());
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}
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qcsat.prepare();
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while (!bits_queue.empty())
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{
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
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one_hot_wires.insert(bit.wire);
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log(" Common input cone for all EN signals: %d cells.\n", GetSize(qcsat.imported_cells));
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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bits_queue.clear();
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
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sat_cells.insert(pbit.cell);
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}
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}
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for (auto wire : one_hot_wires) {
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log(" Adding one-hot constraint for wire %s.\n", log_id(wire));
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vector<int> ez_wire_bits = satgen.importSigSpec(wire);
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for (int i : ez_wire_bits)
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for (int j : ez_wire_bits)
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if (i != j) ez->assume(ez->NOT(i), j);
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}
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log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
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for (auto cell : sat_cells)
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satgen.importCell(cell);
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());
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// now try merging the ports.
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@ -422,14 +385,14 @@ struct MemoryShareWorker
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if (port2.removed)
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continue;
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if (ez->solve(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2))) {
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if (qcsat.ez->solve(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2))) {
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log(" According to SAT solver sharing of port %d with port %d is not possible.\n", idx1, idx2);
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continue;
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}
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log(" Merging port %d into port %d.\n", idx2, idx1);
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mem.prepare_wr_merge(idx1, idx2);
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port_to_sat_variable.at(idx1) = ez->OR(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2));
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port_to_sat_variable.at(idx1) = qcsat.ez->OR(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2));
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RTLIL::SigSpec last_addr = port1.addr;
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RTLIL::SigSpec last_data = port1.data;
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@ -511,21 +474,7 @@ struct MemoryShareWorker
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while (consolidate_wr_by_addr(mem));
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}
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cone_ct.setup_internals();
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cone_ct.cell_types.erase(ID($mul));
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cone_ct.cell_types.erase(ID($mod));
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cone_ct.cell_types.erase(ID($div));
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cone_ct.cell_types.erase(ID($modfloor));
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cone_ct.cell_types.erase(ID($divfloor));
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cone_ct.cell_types.erase(ID($pow));
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cone_ct.cell_types.erase(ID($shl));
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cone_ct.cell_types.erase(ID($shr));
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cone_ct.cell_types.erase(ID($sshl));
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cone_ct.cell_types.erase(ID($sshr));
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cone_ct.cell_types.erase(ID($shift));
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cone_ct.cell_types.erase(ID($shiftx));
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modwalker.setup(module, &cone_ct);
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modwalker.setup(module);
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for (auto &mem : memories)
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consolidate_wr_using_sat(mem);
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@ -21,7 +21,8 @@
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/satgen.h"
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#include "kernel/qcsat.h"
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#include "kernel/modtools.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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@ -51,26 +52,23 @@ struct OptDffWorker
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FfInitVals initvals;
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dict<SigBit, int> bitusers;
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dict<SigBit, cell_int_t> bit2mux;
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dict<SigBit, RTLIL::Cell*> bit2driver;
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typedef std::map<RTLIL::SigBit, bool> pattern_t;
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typedef std::set<pattern_t> patterns_t;
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typedef std::pair<RTLIL::SigBit, bool> ctrl_t;
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typedef std::set<ctrl_t> ctrls_t;
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ezSatPtr ez;
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SatGen satgen;
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pool<Cell*> sat_cells;
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ModWalker modwalker;
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QuickConeSat qcsat;
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// Used as a queue.
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std::vector<Cell *> dff_cells;
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OptDffWorker(const OptDffOptions &opt, Module *mod) : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod), ez(), satgen(ez.get(), &sigmap) {
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// Gathering three kinds of information here for every sigmapped SigBit:
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OptDffWorker(const OptDffOptions &opt, Module *mod) : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod), modwalker(module->design, module), qcsat(modwalker) {
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// Gathering two kinds of information here for every sigmapped SigBit:
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//
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// - bitusers: how many users it has (muxes will only be merged into FFs if this is 1, making the FF the only user)
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// - bit2mux: the mux cell and bit index that drives it, if any
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// - bit2driver: the cell driving it, if any
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for (auto wire : module->wires())
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{
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@ -88,10 +86,6 @@ struct OptDffWorker
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for (auto conn : cell->connections()) {
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bool is_output = cell->output(conn.first);
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if (is_output) {
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for (auto bit : sigmap(conn.second))
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bit2driver[bit] = cell;
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}
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if (!is_output || !cell->known()) {
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for (auto bit : sigmap(conn.second))
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bitusers[bit]++;
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@ -104,20 +98,6 @@ struct OptDffWorker
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}
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std::function<void(Cell*)> sat_import_cell = [&](Cell *c) {
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if (!sat_cells.insert(c).second)
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return;
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if (!satgen.importCell(c))
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return;
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for (auto &conn : c->connections()) {
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if (!c->input(conn.first))
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continue;
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for (auto bit : sigmap(conn.second))
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if (bit2driver.count(bit))
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sat_import_cell(bit2driver.at(bit));
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}
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};
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State combine_const(State a, State b) {
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if (a == State::Sx && !opt.keepdc)
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return b;
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|
|
@ -594,19 +574,19 @@ struct OptDffWorker
|
|||
if (!opt.sat)
|
||||
continue;
|
||||
// For each register bit, try to prove that it cannot change from the initial value. If so, remove it
|
||||
if (!bit2driver.count(ff.sig_d[i]))
|
||||
if (!modwalker.has_drivers(ff.sig_d.extract(i)))
|
||||
continue;
|
||||
if (val != State::S0 && val != State::S1)
|
||||
continue;
|
||||
|
||||
sat_import_cell(bit2driver.at(ff.sig_d[i]));
|
||||
int init_sat_pi = qcsat.importSigBit(val);
|
||||
int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]);
|
||||
int d_sat_pi = qcsat.importSigBit(ff.sig_d[i]);
|
||||
|
||||
int init_sat_pi = satgen.importSigSpec(val).front();
|
||||
int q_sat_pi = satgen.importSigBit(ff.sig_q[i]);
|
||||
int d_sat_pi = satgen.importSigBit(ff.sig_d[i]);
|
||||
qcsat.prepare();
|
||||
|
||||
// Try to find out whether the register bit can change under some circumstances
|
||||
bool counter_example_found = ez->solve(ez->IFF(q_sat_pi, init_sat_pi), ez->NOT(ez->IFF(d_sat_pi, init_sat_pi)));
|
||||
bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi)));
|
||||
|
||||
// If the register bit cannot change, we can replace it with a constant
|
||||
if (counter_example_found)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/satgen.h"
|
||||
#include "kernel/qcsat.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/modtools.h"
|
||||
#include "kernel/utils.h"
|
||||
|
|
@ -58,8 +58,6 @@ struct ShareWorker
|
|||
std::map<RTLIL::Cell*, std::set<RTLIL::Cell*, cell_ptr_cmp>, cell_ptr_cmp> topo_cell_drivers;
|
||||
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*, cell_ptr_cmp>> topo_bit_drivers;
|
||||
|
||||
std::vector<std::pair<RTLIL::SigBit, RTLIL::SigBit>> exclusive_ctrls;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------
|
||||
// Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree
|
||||
|
|
@ -1156,7 +1154,6 @@ struct ShareWorker
|
|||
recursion_state.clear();
|
||||
topo_cell_drivers.clear();
|
||||
topo_bit_drivers.clear();
|
||||
exclusive_ctrls.clear();
|
||||
terminal_bits.clear();
|
||||
shareable_cells.clear();
|
||||
forbidden_controls_cache.clear();
|
||||
|
|
@ -1171,13 +1168,6 @@ struct ShareWorker
|
|||
log("Found %d cells in module %s that may be considered for resource sharing.\n",
|
||||
GetSize(shareable_cells), log_id(module));
|
||||
|
||||
for (auto cell : module->cells())
|
||||
if (cell->type == ID($pmux))
|
||||
for (auto bit : cell->getPort(ID::S))
|
||||
for (auto other_bit : cell->getPort(ID::S))
|
||||
if (bit < other_bit)
|
||||
exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));
|
||||
|
||||
while (!shareable_cells.empty() && config.limit != 0)
|
||||
{
|
||||
RTLIL::Cell *cell = *shareable_cells.begin();
|
||||
|
|
@ -1256,8 +1246,11 @@ struct ShareWorker
|
|||
optimize_activation_patterns(filtered_cell_activation_patterns);
|
||||
optimize_activation_patterns(filtered_other_cell_activation_patterns);
|
||||
|
||||
ezSatPtr ez;
|
||||
SatGen satgen(ez.get(), &modwalker.sigmap);
|
||||
QuickConeSat qcsat(modwalker);
|
||||
if (config.opt_fast) {
|
||||
qcsat.max_cell_outs = 3;
|
||||
qcsat.max_cell_count = 100;
|
||||
}
|
||||
|
||||
pool<RTLIL::Cell*> sat_cells;
|
||||
std::set<RTLIL::SigBit> bits_queue;
|
||||
|
|
@ -1267,77 +1260,45 @@ struct ShareWorker
|
|||
|
||||
for (auto &p : filtered_cell_activation_patterns) {
|
||||
log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
|
||||
cell_active.push_back(ez->vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
|
||||
cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
|
||||
all_ctrl_signals.append(p.first);
|
||||
}
|
||||
|
||||
for (auto &p : filtered_other_cell_activation_patterns) {
|
||||
log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
|
||||
other_cell_active.push_back(ez->vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
|
||||
other_cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
|
||||
all_ctrl_signals.append(p.first);
|
||||
}
|
||||
|
||||
for (auto &bit : cell_activation_signals.to_sigbit_vector())
|
||||
bits_queue.insert(bit);
|
||||
qcsat.prepare();
|
||||
|
||||
for (auto &bit : other_cell_activation_signals.to_sigbit_vector())
|
||||
bits_queue.insert(bit);
|
||||
|
||||
while (!bits_queue.empty())
|
||||
{
|
||||
pool<ModWalker::PortBit> portbits;
|
||||
modwalker.get_drivers(portbits, bits_queue);
|
||||
bits_queue.clear();
|
||||
|
||||
for (auto &pbit : portbits)
|
||||
if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
|
||||
if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4)
|
||||
continue;
|
||||
// log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type));
|
||||
bits_queue.insert(modwalker.cell_inputs[pbit.cell].begin(), modwalker.cell_inputs[pbit.cell].end());
|
||||
satgen.importCell(pbit.cell);
|
||||
sat_cells.insert(pbit.cell);
|
||||
}
|
||||
|
||||
if (config.opt_fast && sat_cells.size() > 100)
|
||||
break;
|
||||
}
|
||||
|
||||
for (auto it : exclusive_ctrls)
|
||||
if (satgen.importedSigBit(it.first) && satgen.importedSigBit(it.second)) {
|
||||
log(" Adding exclusive control bits: %s vs. %s\n", log_signal(it.first), log_signal(it.second));
|
||||
int sub1 = satgen.importSigBit(it.first);
|
||||
int sub2 = satgen.importSigBit(it.second);
|
||||
ez->assume(ez->NOT(ez->AND(sub1, sub2)));
|
||||
}
|
||||
|
||||
if (!ez->solve(ez->expression(ez->OpOr, cell_active))) {
|
||||
int sub1 = qcsat.ez->expression(qcsat.ez->OpOr, cell_active);
|
||||
if (!qcsat.ez->solve(sub1)) {
|
||||
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell));
|
||||
cells_to_remove.insert(cell);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!ez->solve(ez->expression(ez->OpOr, other_cell_active))) {
|
||||
int sub2 = qcsat.ez->expression(qcsat.ez->OpOr, other_cell_active);
|
||||
if (!qcsat.ez->solve(sub2)) {
|
||||
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell));
|
||||
cells_to_remove.insert(other_cell);
|
||||
shareable_cells.erase(other_cell);
|
||||
continue;
|
||||
}
|
||||
|
||||
ez->non_incremental();
|
||||
qcsat.ez->non_incremental();
|
||||
|
||||
all_ctrl_signals.sort_and_unify();
|
||||
std::vector<int> sat_model = satgen.importSigSpec(all_ctrl_signals);
|
||||
std::vector<int> sat_model = qcsat.importSig(all_ctrl_signals);
|
||||
std::vector<bool> sat_model_values;
|
||||
|
||||
int sub1 = ez->expression(ez->OpOr, cell_active);
|
||||
int sub2 = ez->expression(ez->OpOr, other_cell_active);
|
||||
ez->assume(ez->AND(sub1, sub2));
|
||||
qcsat.ez->assume(qcsat.ez->AND(sub1, sub2));
|
||||
|
||||
log(" Size of SAT problem: %d cells, %d variables, %d clauses\n",
|
||||
GetSize(sat_cells), ez->numCnfVariables(), ez->numCnfClauses());
|
||||
GetSize(sat_cells), qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());
|
||||
|
||||
if (ez->solve(sat_model, sat_model_values)) {
|
||||
if (qcsat.ez->solve(sat_model, sat_model_values)) {
|
||||
log(" According to the SAT solver this pair of cells can not be shared.\n");
|
||||
log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), GetSize(sat_model_values));
|
||||
for (int i = GetSize(sat_model_values)-1; i >= 0; i--)
|
||||
|
|
|
|||
Loading…
Reference in New Issue