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Merge pull request #2368 from YosysHQ/verific_portrange 

Fix import of VHDL enums
This commit is contained in:
clairexen 2020-08-31 11:58:29 +02:00 committed by GitHub
parent 3030c2b46c 3af499c60f
commit d23e4b4dce
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 20 additions and 11 deletions
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25
frontends/verific/verific.cc
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@ -199,12 +199,17 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k)); attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k));
} }
else if (nl->IsFromVhdl()) { else if (nl->IsFromVhdl()) {
// Expect "<binary>" // Expect "<binary>" or plain <binary>
auto p = v; auto p = v;
if (p) { if (p) {
if (*p != '"') if (*p != '"') {
p = nullptr; auto l = strlen(p);
else { auto q = (char*)malloc(l+1);
strncpy(q, p, l);
q[l] = '\0';
for(char *ptr = q; *ptr; ++ptr )*ptr = tolower(*ptr);
attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
} else {
auto *q = p+1; auto *q = p+1;
for (; *q != '"'; q++) for (; *q != '"'; q++)
if (*q != '0' && *q != '1') { if (*q != '0' && *q != '1') {
@ -213,10 +218,9 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
} }
if (p && *(q+1) != '\0') if (p && *(q+1) != '\0')
p = nullptr; p = nullptr;
}
} if (p != nullptr)
if (p == nullptr) {
log_error("Expected TypeRange value '%s' to be of form \"<binary>\".\n", v);
auto l = strlen(p); auto l = strlen(p);
auto q = (char*)malloc(l+1-2); auto q = (char*)malloc(l+1-2);
strncpy(q, p+1, l-2); strncpy(q, p+1, l-2);
@ -226,6 +230,11 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
} }
} }
} }
if (p == nullptr)
log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v);
}
}
}
} }
RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst) RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst)