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Merge pull request #1747 from YosysHQ/claire/partselfix 

Fix partsel expr bit width handling and add test case
This commit is contained in:
Eddie Hung 2020-03-09 11:51:57 -07:00 committed by GitHub
parent 282d331e7e a7cc4673c3
commit d23acf8c61
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2 changed files with 10 additions and 4 deletions
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10
frontends/verilog/verilog_parser.y
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@ -593,13 +593,15 @@ non_opt_range:
} |
'[' expr TOK_POS_INDEXED expr ']' {
$$ = new AstNode(AST_RANGE);
$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
AstNode *expr = new AstNode(AST_CONCAT, $2);
$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
$$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
} |
'[' expr TOK_NEG_INDEXED expr ']' {
$$ = new AstNode(AST_RANGE);
$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
AstNode *expr = new AstNode(AST_CONCAT, $2);
$$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
} |
'[' expr ']' {
$$ = new AstNode(AST_RANGE);

4
tests/simple/partsel.v
View File

@ -60,3 +60,7 @@ always @(posedge clk) begin
end
endmodule
module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
assign dout = din[a*b +: 2];
endmodule