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Adding (* techmap_autopurge *) to FD* in abc9_map.v

This commit is contained in:
Eddie Hung 2020-01-14 12:22:21 -08:00
parent 53a99ade9c
commit d21262ee04
1 changed files with 8 additions and 8 deletions
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16
techlibs/xilinx/abc9_map.v
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@ -74,7 +74,7 @@
// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback // (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
// into the (combinatorial) FD* cell to facilitate clock-enable behaviour // into the (combinatorial) FD* cell to facilitate clock-enable behaviour
module FDRE (output Q, input C, CE, D, R); module FDRE (output Q, (* techmap_autopurge *) input C, CE, D, R);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -110,7 +110,7 @@ module FDRE (output Q, input C, CE, D, R);
wire [0:0] abc9_ff.init = 1'b0; wire [0:0] abc9_ff.init = 1'b0;
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule endmodule
module FDRE_1 (output Q, input C, CE, D, R); module FDRE_1 (output Q, (* techmap_autopurge *) input C, CE, D, R);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
wire QQ, $Q; wire QQ, $Q;
generate if (INIT == 1'b1) begin generate if (INIT == 1'b1) begin
@ -138,7 +138,7 @@ module FDRE_1 (output Q, input C, CE, D, R);
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule endmodule
module FDSE (output Q, input C, CE, D, S); module FDSE (output Q, (* techmap_autopurge *) input C, CE, D, S);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -173,7 +173,7 @@ module FDSE (output Q, input C, CE, D, S);
wire [0:0] abc9_ff.init = 1'b0; wire [0:0] abc9_ff.init = 1'b0;
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule endmodule
module FDSE_1 (output Q, input C, CE, D, S); module FDSE_1 (output Q, (* techmap_autopurge *) input C, CE, D, S);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
wire QQ, $Q; wire QQ, $Q;
generate if (INIT == 1'b1) begin generate if (INIT == 1'b1) begin
@ -200,7 +200,7 @@ module FDSE_1 (output Q, input C, CE, D, S);
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule endmodule
module FDCE (output Q, input C, CE, D, CLR); module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -249,7 +249,7 @@ module FDCE (output Q, input C, CE, D, CLR);
wire [0:0] abc9_ff.init = 1'b0; wire [0:0] abc9_ff.init = 1'b0;
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule endmodule
module FDCE_1 (output Q, input C, CE, D, CLR); module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
wire QQ, $Q, $QQ; wire QQ, $Q, $QQ;
generate if (INIT == 1'b1) begin generate if (INIT == 1'b1) begin
@ -288,7 +288,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule endmodule
module FDPE (output Q, input C, CE, D, PRE); module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
@ -335,7 +335,7 @@ module FDPE (output Q, input C, CE, D, PRE);
wire [0:0] abc9_ff.init = 1'b0; wire [0:0] abc9_ff.init = 1'b0;
wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule endmodule
module FDPE_1 (output Q, input C, CE, D, PRE); module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
wire QQ, $Q, $QQ; wire QQ, $Q, $QQ;
generate if (INIT == 1'b1) begin generate if (INIT == 1'b1) begin