diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 155de8f90..dc8f39e8d 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1138,7 +1138,8 @@ ignspec_expr:
 	};
 
 ignspec_id:
-	TOK_ID { delete $1; };
+	TOK_ID { delete $1; }
+	range_or_multirange { delete $3; };
 
 /**********************************************************************/
 
diff --git a/tests/various/specify.v b/tests/various/specify.v
index 5655ded21..c160d2ec4 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -55,3 +55,10 @@ specify
   $setup(d, posedge clk &&& e, 1:2:3);
 endspecify
 endmodule
+
+module test6(input clk, d, e, output q);
+specify
+  (d[0] *> q[0]) = (3,1);
+  (posedge clk[0] => (q[0] +: d[0])) = (3,1);
+endspecify
+endmodule