Update manual

This commit is contained in:
Miodrag Milanovic 2022-06-10 15:00:07 +02:00
parent 1940bf647f
commit d1cd24a457
1 changed files with 8 additions and 0 deletions

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@ -7838,6 +7838,11 @@ Add Verilog library directories. Verific will search in this directories to
find undefined modules.
verific -vlog-libext <extension>..
Add Verilog library extensions, used when searching in library directories.
verific -vlog-define <macro>[=<value>]..
Add Verilog defines.
@ -8057,6 +8062,9 @@ Options:
Do not change the width of memory address ports. Use this options in
flows that use the 'memory_memx' pass.
-mux_undef
remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
-keepdc
Do not optimize explicit don't-care values.
\end{lstlisting}