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Removed alu and div_mod tests as agreed

This commit is contained in:
Miodrag Milanovic 2019-10-04 08:41:53 +02:00
parent 1caaf51492
commit d19f765a58
4 changed files with 0 additions and 57 deletions
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19
tests/ecp5/alu.v
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@ -1,19 +0,0 @@
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule

13
tests/ecp5/alu.ys
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@ -1,13 +0,0 @@
read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 32 t:CCU2C
select -assert-count 242 t:L6MUX21
select -assert-count 1127 t:LUT4
select -assert-count 417 t:PFUMX
select -assert-count 32 t:TRELLIS_FF
select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D

13
tests/ecp5/div_mod.v
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@ -1,13 +0,0 @@
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x % y;
assign B = x / y;
endmodule

12
tests/ecp5/div_mod.ys
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@ -1,12 +0,0 @@
read_verilog div_mod.v
hierarchy -top top
flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 28 t:CCU2C
select -assert-count 26 t:L6MUX21
select -assert-count 138 t:LUT4
select -assert-count 60 t:PFUMX
select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D