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Merge pull request #1299 from YosysHQ/eddie/cleanup2 

More cleanup, more use of ID() inside passes/techmap
This commit is contained in:
Clifford Wolf 2019-08-15 22:56:32 +02:00 committed by GitHub
parent d8a2aaa463 6cd8cace0c
commit d16178f233
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
33 changed files with 1175 additions and 1182 deletions
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2
frontends/blif/blifparse.cc
View File

@ -78,7 +78,7 @@ failed:
return std::pair<RTLIL::IdString, int>("\\" + name, 0); return std::pair<RTLIL::IdString, int>("\\" + name, 0);
} }
void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bool run_clean, bool sop_mode, bool wideports) void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool run_clean, bool sop_mode, bool wideports)
{ {
RTLIL::Module *module = nullptr; RTLIL::Module *module = nullptr;
RTLIL::Const *lutptr = NULL; RTLIL::Const *lutptr = NULL;

2
frontends/blif/blifparse.h
View File

@ -24,7 +24,7 @@
YOSYS_NAMESPACE_BEGIN YOSYS_NAMESPACE_BEGIN
extern void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, extern void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name,
bool run_clean = false, bool sop_mode = false, bool wideports = false); bool run_clean = false, bool sop_mode = false, bool wideports = false);
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

51
kernel/satgen.h
View File

@ -293,7 +293,7 @@ struct SatGen
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
int undef_y_bit = ez->OR(undef_any_a, undef_any_b); int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
if (cell->type == ID($div) || cell->type == ID($mod)) { if (cell->type.in(ID($div), ID($mod))) {
std::vector<int> b = importSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> b = importSigSpec(cell->getPort(ID(B)), timestep);
undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
} }
@ -320,17 +320,17 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (cell->type == ID($and) || cell->type == ID($_AND_)) if (cell->type.in(ID($and), ID($_AND_)))
ez->assume(ez->vec_eq(ez->vec_and(a, b), yy)); ez->assume(ez->vec_eq(ez->vec_and(a, b), yy));
if (cell->type == ID($_NAND_)) if (cell->type == ID($_NAND_))
ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy)); ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy));
if (cell->type == ID($or) || cell->type == ID($_OR_)) if (cell->type.in(ID($or), ID($_OR_)))
ez->assume(ez->vec_eq(ez->vec_or(a, b), yy)); ez->assume(ez->vec_eq(ez->vec_or(a, b), yy));
if (cell->type == ID($_NOR_)) if (cell->type == ID($_NOR_))
ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy)); ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy));
if (cell->type == ID($xor) || cell->type == ID($_XOR_)) if (cell->type.in(ID($xor), ID($_XOR_)))
ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy)); ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy));
if (cell->type == ID($xnor) || cell->type == ID($_XNOR_)) if (cell->type.in(ID($xnor), ID($_XNOR_)))
ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy)); ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy));
if (cell->type == ID($_ANDNOT_)) if (cell->type == ID($_ANDNOT_))
ez->assume(ez->vec_eq(ez->vec_and(a, ez->vec_not(b)), yy)); ez->assume(ez->vec_eq(ez->vec_and(a, ez->vec_not(b)), yy));
@ -456,7 +456,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($_NOT_) || cell->type == ID($not)) if (cell->type.in(ID($_NOT_), ID($not)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
@ -475,7 +475,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($_MUX_) || cell->type == ID($mux) || cell->type == ID($_NMUX_)) if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
@ -555,7 +555,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($pos) || cell->type == ID($neg)) if (cell->type.in(ID($pos), ID($neg)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
@ -589,8 +589,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($reduce_and) || cell->type == ID($reduce_or) || cell->type == ID($reduce_xor) || if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
cell->type == ID($reduce_xnor) || cell->type == ID($reduce_bool) || cell->type == ID($logic_not))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
@ -599,7 +598,7 @@ struct SatGen
if (cell->type == ID($reduce_and)) if (cell->type == ID($reduce_and))
ez->SET(ez->expression(ez->OpAnd, a), yy.at(0)); ez->SET(ez->expression(ez->OpAnd, a), yy.at(0));
if (cell->type == ID($reduce_or) || cell->type == ID($reduce_bool)) if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
ez->SET(ez->expression(ez->OpOr, a), yy.at(0)); ez->SET(ez->expression(ez->OpOr, a), yy.at(0));
if (cell->type == ID($reduce_xor)) if (cell->type == ID($reduce_xor))
ez->SET(ez->expression(ez->OpXor, a), yy.at(0)); ez->SET(ez->expression(ez->OpXor, a), yy.at(0));
@ -620,11 +619,11 @@ struct SatGen
int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a))); int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)));
ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0))); ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0)));
} }
else if (cell->type == ID($reduce_or) || cell->type == ID($reduce_bool) || cell->type == ID($logic_not)) { else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a))); int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a)));
ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0))); ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0)));
} }
else if (cell->type == ID($reduce_xor) || cell->type == ID($reduce_xnor)) { else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
ez->assume(ez->IFF(aX, undef_y.at(0))); ez->assume(ez->IFF(aX, undef_y.at(0)));
} else } else
log_abort(); log_abort();
@ -637,7 +636,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($logic_and) || cell->type == ID($logic_or)) if (cell->type.in(ID($logic_and), ID($logic_or)))
{ {
std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep);
@ -683,7 +682,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($lt) || cell->type == ID($le) || cell->type == ID($eq) || cell->type == ID($ne) || cell->type == ID($eqx) || cell->type == ID($nex) || cell->type == ID($ge) || cell->type == ID($gt)) if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
{ {
bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
@ -693,7 +692,7 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef && (cell->type == ID($eqx) || cell->type == ID($nex))) { if (model_undef && cell->type.in(ID($eqx), ID($nex))) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
extendSignalWidth(undef_a, undef_b, cell, true); extendSignalWidth(undef_a, undef_b, cell, true);
@ -705,9 +704,9 @@ struct SatGen
ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0)); ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0));
if (cell->type == ID($le)) if (cell->type == ID($le))
ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0)); ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0));
if (cell->type == ID($eq) || cell->type == ID($eqx)) if (cell->type.in(ID($eq), ID($eqx)))
ez->SET(ez->vec_eq(a, b), yy.at(0)); ez->SET(ez->vec_eq(a, b), yy.at(0));
if (cell->type == ID($ne) || cell->type == ID($nex)) if (cell->type.in(ID($ne), ID($nex)))
ez->SET(ez->vec_ne(a, b), yy.at(0)); ez->SET(ez->vec_ne(a, b), yy.at(0));
if (cell->type == ID($ge)) if (cell->type == ID($ge))
ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0)); ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0));
@ -716,7 +715,7 @@ struct SatGen
for (size_t i = 1; i < y.size(); i++) for (size_t i = 1; i < y.size(); i++)
ez->SET(ez->CONST_FALSE, yy.at(i)); ez->SET(ez->CONST_FALSE, yy.at(i));
if (model_undef && (cell->type == ID($eqx) || cell->type == ID($nex))) if (model_undef && cell->type.in(ID($eqx), ID($nex)))
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
@ -733,7 +732,7 @@ struct SatGen
ez->assume(ez->vec_eq(y, yy)); ez->assume(ez->vec_eq(y, yy));
} }
else if (model_undef && (cell->type == ID($eq) || cell->type == ID($ne))) else if (model_undef && cell->type.in(ID($eq), ID($ne)))
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
@ -767,7 +766,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($shl) || cell->type == ID($shr) || cell->type == ID($sshl) || cell->type == ID($sshr) || cell->type == ID($shift) || cell->type == ID($shiftx)) if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
@ -786,7 +785,7 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> shifted_a; std::vector<int> shifted_a;
if (cell->type == ID($shl) || cell->type == ID($sshl)) if (cell->type.in( ID($shl), ID($sshl)))
shifted_a = ez->vec_shift_left(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); shifted_a = ez->vec_shift_left(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shr)) if (cell->type == ID($shr))
@ -795,7 +794,7 @@ struct SatGen
if (cell->type == ID($sshr)) if (cell->type == ID($sshr))
shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shift) || cell->type == ID($shiftx)) if (cell->type.in(ID($shift), ID($shiftx)))
shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
ez->assume(ez->vec_eq(shifted_a, yy)); ez->assume(ez->vec_eq(shifted_a, yy));
@ -816,7 +815,7 @@ struct SatGen
while (undef_y.size() > undef_a.size()) while (undef_y.size() > undef_a.size())
undef_a.push_back(extend_bit); undef_a.push_back(extend_bit);
if (cell->type == ID($shl) || cell->type == ID($sshl)) if (cell->type.in(ID($shl), ID($sshl)))
undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shr)) if (cell->type == ID($shr))
@ -936,7 +935,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($div) || cell->type == ID($mod)) if (cell->type.in(ID($div), ID($mod)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
@ -1356,7 +1355,7 @@ struct SatGen
return true; return true;
} }
if (cell->type == ID($_BUF_) || cell->type == ID($equiv)) if (cell->type.in(ID($_BUF_), ID($equiv)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);

2
passes/cmds/delete.cc
View File

@ -107,7 +107,7 @@ struct DeletePass : public Pass {
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
if (design->selected(module, it.second)) if (design->selected(module, it.second))
delete_cells.insert(it.second); delete_cells.insert(it.second);
if ((it.second->type == "$memrd" || it.second->type == "$memwr") && if (it.second->type.in("$memrd", "$memwr") &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0) delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
delete_cells.insert(it.second); delete_cells.insert(it.second);
} }

40
passes/opt/opt_expr.cc
View File

@ -478,19 +478,19 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (detect_const_and && (found_zero || found_inv)) { if (detect_const_and && (found_zero || found_inv)) {
cover("opt.opt_expr.const_and"); cover("opt.opt_expr.const_and");
replace_cell(assign_map, module, cell, "const_and", "\\Y", RTLIL::State::S0); replace_cell(assign_map, module, cell, "const_and", ID(Y), RTLIL::State::S0);
goto next_cell; goto next_cell;
} }
if (detect_const_or && (found_one || found_inv)) { if (detect_const_or && (found_one || found_inv)) {
cover("opt.opt_expr.const_or"); cover("opt.opt_expr.const_or");
replace_cell(assign_map, module, cell, "const_or", "\\Y", RTLIL::State::S1); replace_cell(assign_map, module, cell, "const_or", ID(Y), RTLIL::State::S1);
goto next_cell; goto next_cell;
} }
if (non_const_input != State::Sm && !found_undef) { if (non_const_input != State::Sm && !found_undef) {
cover("opt.opt_expr.and_or_buffer"); cover("opt.opt_expr.and_or_buffer");
replace_cell(assign_map, module, cell, "and_or_buffer", "\\Y", non_const_input); replace_cell(assign_map, module, cell, "and_or_buffer", ID(Y), non_const_input);
goto next_cell; goto next_cell;
} }
} }
@ -506,7 +506,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
did_something = true; did_something = true;
} else { } else {
cover("opt.opt_expr.unary_buffer"); cover("opt.opt_expr.unary_buffer");
replace_cell(assign_map, module, cell, "unary_buffer", "\\Y", cell->getPort("\\A")); replace_cell(assign_map, module, cell, "unary_buffer", ID(Y), cell->getPort(ID(A)));
} }
goto next_cell; goto next_cell;
} }
@ -669,13 +669,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type == "$alu") if (cell->type == "$alu")
{ {
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
RTLIL::SigBit sig_ci = assign_map(cell->getPort("\\CI")); RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI)));
RTLIL::SigBit sig_bi = assign_map(cell->getPort("\\BI")); RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI)));
RTLIL::SigSpec sig_x = cell->getPort("\\X"); RTLIL::SigSpec sig_x = cell->getPort(ID(X));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
RTLIL::SigSpec sig_co = cell->getPort("\\CO"); RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
if (sig_ci.wire || sig_bi.wire) if (sig_ci.wire || sig_bi.wire)
goto next_cell; goto next_cell;
@ -704,11 +704,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
if (i > 0) { if (i > 0) {
cover("opt.opt_expr.fine.$alu"); cover("opt.opt_expr.fine.$alu");
cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort(ID(A), sig_a.extract_end(i));
cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort(ID(B), sig_b.extract_end(i));
cell->setPort("\\X", sig_x.extract_end(i)); cell->setPort(ID(X), sig_x.extract_end(i));
cell->setPort("\\Y", sig_y.extract_end(i)); cell->setPort(ID(Y), sig_y.extract_end(i));
cell->setPort("\\CO", sig_co.extract_end(i)); cell->setPort(ID(CO), sig_co.extract_end(i));
cell->fixup_parameters(); cell->fixup_parameters();
did_something = true; did_something = true;
} }
@ -737,9 +737,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str()); "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str());
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt))) if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); replace_cell(assign_map, module, cell, "x-bit in input", ID(Y), RTLIL::State::Sx);
else else
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size())); replace_cell(assign_map, module, cell, "x-bit in input", ID(Y), RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort(ID(Y)).size()));
goto next_cell; goto next_cell;
} }
} }
@ -747,7 +747,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID(Y)).size() == 1 && if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID(Y)).size() == 1 &&
invert_map.count(assign_map(cell->getPort(ID(A)))) != 0) { invert_map.count(assign_map(cell->getPort(ID(A)))) != 0) {
cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); replace_cell(assign_map, module, cell, "double_invert", ID(Y), invert_map.at(assign_map(cell->getPort(ID(A)))));
goto next_cell; goto next_cell;
} }
@ -890,7 +890,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false); new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y); replace_cell(assign_map, module, cell, "isneq", ID(Y), new_y);
goto next_cell; goto next_cell;
} }
if (a[i] == b[i]) if (a[i] == b[i])

2
passes/sat/expose.cc
View File

@ -143,7 +143,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
continue; continue;
} }
if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") { if (info.cell->type.in("$_DFF_N_", "$_DFF_P_")) {
info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit(); info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
info.clk_polarity = info.cell->type == "$_DFF_P_"; info.clk_polarity = info.cell->type == "$_DFF_P_";
info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit(); info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();

396
passes/techmap/abc.cc
View File

@ -166,39 +166,39 @@ void mark_port(RTLIL::SigSpec sig)
void extract_cell(RTLIL::Cell *cell, bool keepff) void extract_cell(RTLIL::Cell *cell, bool keepff)
{ {
if (cell->type.in("$_DFF_N_", "$_DFF_P_")) if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{ {
if (clk_polarity != (cell->type == "$_DFF_P_")) if (clk_polarity != (cell->type == ID($_DFF_P_)))
return; return;
if (clk_sig != assign_map(cell->getPort("\\C"))) if (clk_sig != assign_map(cell->getPort(ID(C))))
return; return;
if (GetSize(en_sig) != 0) if (GetSize(en_sig) != 0)
return; return;
goto matching_dff; goto matching_dff;
} }
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_")) if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{ {
if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_")) if (clk_polarity != cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)))
return; return;
if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_")) if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
return; return;
if (clk_sig != assign_map(cell->getPort("\\C"))) if (clk_sig != assign_map(cell->getPort(ID(C))))
return; return;
if (en_sig != assign_map(cell->getPort("\\E"))) if (en_sig != assign_map(cell->getPort(ID(E))))
return; return;
goto matching_dff; goto matching_dff;
} }
if (0) { if (0) {
matching_dff: matching_dff:
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
if (keepff) if (keepff)
for (auto &c : sig_q.chunks()) for (auto &c : sig_q.chunks())
if (c.wire != NULL) if (c.wire != NULL)
c.wire->attributes["\\keep"] = 1; c.wire->attributes[ID(keep)] = 1;
assign_map.apply(sig_d); assign_map.apply(sig_d);
assign_map.apply(sig_q); assign_map.apply(sig_q);
@ -209,25 +209,25 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
return; return;
} }
if (cell->type.in("$_BUF_", "$_NOT_")) if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
assign_map.apply(sig_a); assign_map.apply(sig_a);
assign_map.apply(sig_y); assign_map.apply(sig_y);
map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a)); map_signal(sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(sig_a));
module->remove(cell); module->remove(cell);
return; return;
} }
if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
assign_map.apply(sig_a); assign_map.apply(sig_a);
assign_map.apply(sig_b); assign_map.apply(sig_b);
@ -236,21 +236,21 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
int mapped_a = map_signal(sig_a); int mapped_a = map_signal(sig_a);
int mapped_b = map_signal(sig_b); int mapped_b = map_signal(sig_b);
if (cell->type == "$_AND_") if (cell->type == ID($_AND_))
map_signal(sig_y, G(AND), mapped_a, mapped_b); map_signal(sig_y, G(AND), mapped_a, mapped_b);
else if (cell->type == "$_NAND_") else if (cell->type == ID($_NAND_))
map_signal(sig_y, G(NAND), mapped_a, mapped_b); map_signal(sig_y, G(NAND), mapped_a, mapped_b);
else if (cell->type == "$_OR_") else if (cell->type == ID($_OR_))
map_signal(sig_y, G(OR), mapped_a, mapped_b); map_signal(sig_y, G(OR), mapped_a, mapped_b);
else if (cell->type == "$_NOR_") else if (cell->type == ID($_NOR_))
map_signal(sig_y, G(NOR), mapped_a, mapped_b); map_signal(sig_y, G(NOR), mapped_a, mapped_b);
else if (cell->type == "$_XOR_") else if (cell->type == ID($_XOR_))
map_signal(sig_y, G(XOR), mapped_a, mapped_b); map_signal(sig_y, G(XOR), mapped_a, mapped_b);
else if (cell->type == "$_XNOR_") else if (cell->type == ID($_XNOR_))
map_signal(sig_y, G(XNOR), mapped_a, mapped_b); map_signal(sig_y, G(XNOR), mapped_a, mapped_b);
else if (cell->type == "$_ANDNOT_") else if (cell->type == ID($_ANDNOT_))
map_signal(sig_y, G(ANDNOT), mapped_a, mapped_b); map_signal(sig_y, G(ANDNOT), mapped_a, mapped_b);
else if (cell->type == "$_ORNOT_") else if (cell->type == ID($_ORNOT_))
map_signal(sig_y, G(ORNOT), mapped_a, mapped_b); map_signal(sig_y, G(ORNOT), mapped_a, mapped_b);
else else
log_abort(); log_abort();
@ -259,12 +259,12 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
return; return;
} }
if (cell->type.in("$_MUX_", "$_NMUX_")) if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_s = cell->getPort("\\S"); RTLIL::SigSpec sig_s = cell->getPort(ID(S));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
assign_map.apply(sig_a); assign_map.apply(sig_a);
assign_map.apply(sig_b); assign_map.apply(sig_b);
@ -275,18 +275,18 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
int mapped_b = map_signal(sig_b); int mapped_b = map_signal(sig_b);
int mapped_s = map_signal(sig_s); int mapped_s = map_signal(sig_s);
map_signal(sig_y, cell->type == "$_MUX_" ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s); map_signal(sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
module->remove(cell); module->remove(cell);
return; return;
} }
if (cell->type.in("$_AOI3_", "$_OAI3_")) if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_c = cell->getPort("\\C"); RTLIL::SigSpec sig_c = cell->getPort(ID(C));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
assign_map.apply(sig_a); assign_map.apply(sig_a);
assign_map.apply(sig_b); assign_map.apply(sig_b);
@ -297,19 +297,19 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
int mapped_b = map_signal(sig_b); int mapped_b = map_signal(sig_b);
int mapped_c = map_signal(sig_c); int mapped_c = map_signal(sig_c);
map_signal(sig_y, cell->type == "$_AOI3_" ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c); map_signal(sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
module->remove(cell); module->remove(cell);
return; return;
} }
if (cell->type.in("$_AOI4_", "$_OAI4_")) if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_c = cell->getPort("\\C"); RTLIL::SigSpec sig_c = cell->getPort(ID(C));
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
assign_map.apply(sig_a); assign_map.apply(sig_a);
assign_map.apply(sig_b); assign_map.apply(sig_b);
@ -322,7 +322,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
int mapped_c = map_signal(sig_c); int mapped_c = map_signal(sig_c);
int mapped_d = map_signal(sig_d); int mapped_d = map_signal(sig_d);
map_signal(sig_y, cell->type == "$_AOI4_" ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d); map_signal(sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
module->remove(cell); module->remove(cell);
return; return;
@ -352,23 +352,20 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
auto sig = signal_list.at(sid); auto sig = signal_list.at(sid);
if (sig.bit.wire != nullptr) if (sig.bit.wire != nullptr)
{ {
std::stringstream sstr; std::string s = stringf("$abc$%d$%s", map_autoidx, sig.bit.wire->name.c_str()+1);
sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
if (sig.bit.wire->width != 1) if (sig.bit.wire->width != 1)
sstr << "[" << sig.bit.offset << "]"; s += stringf("[%d]", sig.bit.offset);
if (isnew) if (isnew)
sstr << "_new"; s += "_new";
sstr << postfix; s += postfix;
if (orig_wire != nullptr) if (orig_wire != nullptr)
*orig_wire = sig.bit.wire; *orig_wire = sig.bit.wire;
return sstr.str(); return s;
} }
} }
} }
} }
std::stringstream sstr; return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
return sstr.str();
} }
void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts) void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts)
@ -790,7 +787,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
extract_cell(c, keepff); extract_cell(c, keepff);
for (auto &wire_it : module->wires_) { for (auto &wire_it : module->wires_) {
if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep")) if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID(keep)))
mark_port(RTLIL::SigSpec(wire_it.second)); mark_port(RTLIL::SigSpec(wire_it.second));
} }
@ -939,42 +936,42 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n"); fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_BUF_")); fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOT_")); fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
if (enabled_gates.count("AND")) if (enabled_gates.count("AND"))
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_AND_")); fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
if (enabled_gates.count("NAND")) if (enabled_gates.count("NAND"))
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NAND_")); fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
if (enabled_gates.count("OR")) if (enabled_gates.count("OR"))
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_OR_")); fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
if (enabled_gates.count("NOR")) if (enabled_gates.count("NOR"))
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOR_")); fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
if (enabled_gates.count("XOR")) if (enabled_gates.count("XOR"))
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XOR_")); fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
if (enabled_gates.count("XNOR")) if (enabled_gates.count("XNOR"))
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XNOR_")); fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
if (enabled_gates.count("ANDNOT")) if (enabled_gates.count("ANDNOT"))
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ANDNOT_")); fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
if (enabled_gates.count("ORNOT")) if (enabled_gates.count("ORNOT"))
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ORNOT_")); fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
if (enabled_gates.count("AOI3")) if (enabled_gates.count("AOI3"))
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI3_")); fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
if (enabled_gates.count("OAI3")) if (enabled_gates.count("OAI3"))
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI3_")); fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
if (enabled_gates.count("AOI4")) if (enabled_gates.count("AOI4"))
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI4_")); fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
if (enabled_gates.count("OAI4")) if (enabled_gates.count("OAI4"))
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI4_")); fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
if (enabled_gates.count("MUX")) if (enabled_gates.count("MUX"))
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_MUX_")); fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
if (enabled_gates.count("NMUX")) if (enabled_gates.count("NMUX"))
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_NMUX_")); fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
if (map_mux4) if (map_mux4)
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at("$_MUX_")); fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
if (map_mux8) if (map_mux8)
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at("$_MUX_")); fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
if (map_mux16) if (map_mux16)
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at("$_MUX_")); fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
fclose(f); fclose(f);
if (!lut_costs.empty()) { if (!lut_costs.empty()) {
@ -1019,21 +1016,21 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
bool builtin_lib = liberty_file.empty(); bool builtin_lib = liberty_file.empty();
RTLIL::Design *mapped_design = new RTLIL::Design; RTLIL::Design *mapped_design = new RTLIL::Design;
parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, sop_mode);
ifs.close(); ifs.close();
log_header(design, "Re-integrating ABC results.\n"); log_header(design, "Re-integrating ABC results.\n");
RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; RTLIL::Module *mapped_mod = mapped_design->modules_[ID(netlist)];
if (mapped_mod == NULL) if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n"); log_error("ABC output file does not contain a module `netlist'.\n");
for (auto &it : mapped_mod->wires_) { for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second; RTLIL::Wire *w = it.second;
RTLIL::Wire *orig_wire = nullptr; RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire)); RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
if (orig_wire != nullptr && orig_wire->attributes.count("\\src")) if (orig_wire != nullptr && orig_wire->attributes.count(ID(src)))
wire->attributes["\\src"] = orig_wire->attributes["\\src"]; wire->attributes[ID(src)] = orig_wire->attributes[ID(src)];
if (markgroups) wire->attributes["\\abcgroup"] = map_autoidx; if (markgroups) wire->attributes[ID(abcgroup)] = map_autoidx;
design->select(module, wire); design->select(module, wire);
} }
@ -1043,141 +1040,140 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (builtin_lib) if (builtin_lib)
{ {
cell_stats[RTLIL::unescape_id(c->type)]++; cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\ZERO" || c->type == "\\ONE") { if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn; RTLIL::SigSig conn;
conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]); conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
module->connect(conn); module->connect(conn);
continue; continue;
} }
if (c->type == "\\BUF") { if (c->type == ID(BUF)) {
RTLIL::SigSig conn; RTLIL::SigSig conn;
conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]); conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]);
conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]); conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]);
module->connect(conn); module->connect(conn);
continue; continue;
} }
if (c->type == "\\NOT") { if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" || if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\MUX" || c->type == "\\NMUX") { if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\MUX4") { if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)])); cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\MUX8") { if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)])); cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)])); cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)])); cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)])); cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)])); cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)])); cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\MUX16") { if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)])); cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)])); cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)])); cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)])); cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)])); cell->setPort(ID(I), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(I)).as_wire()->name)]));
cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)])); cell->setPort(ID(J), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(J)).as_wire()->name)]));
cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)])); cell->setPort(ID(K), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(K)).as_wire()->name)]));
cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)])); cell->setPort(ID(L), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(L)).as_wire()->name)]));
cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)])); cell->setPort(ID(M), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(M)).as_wire()->name)]));
cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)])); cell->setPort(ID(N), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(N)).as_wire()->name)]));
cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)])); cell->setPort(ID(O), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(O)).as_wire()->name)]));
cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)])); cell->setPort(ID(P), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(P)).as_wire()->name)]));
cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)])); cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)])); cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)])); cell->setPort(ID(V), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(V)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\AOI3" || c->type == "\\OAI3") { if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\AOI4" || c->type == "\\OAI4") { if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "\\DFF") { if (c->type == ID(DFF)) {
log_assert(clk_sig.size() == 1); log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell; RTLIL::Cell *cell;
if (en_sig.size() == 0) { if (en_sig.size() == 0) {
cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
} else { } else {
log_assert(en_sig.size() == 1); log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
cell->setPort("\\E", en_sig); cell->setPort(ID(E), en_sig);
} }
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)])); cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
cell->setPort("\\C", clk_sig); cell->setPort(ID(C), clk_sig);
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
@ -1185,41 +1181,41 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
else else
cell_stats[RTLIL::unescape_id(c->type)]++; cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") { if (c->type.in(ID(_const0_), ID(_const1_))) {
RTLIL::SigSig conn; RTLIL::SigSig conn;
conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]); conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
module->connect(conn); module->connect(conn);
continue; continue;
} }
if (c->type == "\\_dff_") { if (c->type == ID(_dff_)) {
log_assert(clk_sig.size() == 1); log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell; RTLIL::Cell *cell;
if (en_sig.size() == 0) { if (en_sig.size() == 0) {
cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
} else { } else {
log_assert(en_sig.size() == 1); log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
cell->setPort("\\E", en_sig); cell->setPort(ID(E), en_sig);
} }
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)])); cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
cell->setPort("\\C", clk_sig); cell->setPort(ID(C), clk_sig);
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) { if (c->type == ID($lut) && GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)).as_int() == 2) {
SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; SigSpec my_a = module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)];
SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]; SigSpec my_y = module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)];
module->connect(my_y, my_a); module->connect(my_y, my_a);
continue; continue;
} }
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->parameters = c->parameters; cell->parameters = c->parameters;
for (auto &conn : c->connections()) { for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig; RTLIL::SigSpec newsig;
@ -1244,10 +1240,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (recover_init) if (recover_init)
for (auto wire : mapped_mod->wires()) { for (auto wire : mapped_mod->wires()) {
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID(init))) {
Wire *w = module->wires_[remap_name(wire->name)]; Wire *w = module->wires_[remap_name(wire->name)];
log_assert(w->attributes.count("\\init") == 0); log_assert(w->attributes.count(ID(init)) == 0);
w->attributes["\\init"] = wire->attributes.at("\\init"); w->attributes[ID(init)] = wire->attributes.at(ID(init));
} }
} }
@ -1802,9 +1798,9 @@ struct AbcPass : public Pass {
signal_init.clear(); signal_init.clear();
for (Wire *wire : mod->wires()) for (Wire *wire : mod->wires())
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID(init))) {
SigSpec initsig = assign_map(wire); SigSpec initsig = assign_map(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
switch (initval[i]) { switch (initval[i]) {
case State::S0: case State::S0:
@ -1861,16 +1857,16 @@ struct AbcPass : public Pass {
} }
} }
if (cell->type.in("$_DFF_N_", "$_DFF_P_")) if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{ {
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
} }
else else
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_")) if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{ {
bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"); bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"); bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
} }
else else
continue; continue;

100
passes/techmap/abc9.cc
View File

@ -71,11 +71,9 @@ RTLIL::Module *module;
bool clk_polarity, en_polarity; bool clk_polarity, en_polarity;
RTLIL::SigSpec clk_sig, en_sig; RTLIL::SigSpec clk_sig, en_sig;
std::string remap_name(RTLIL::IdString abc_name) inline std::string remap_name(RTLIL::IdString abc_name)
{ {
std::stringstream sstr; return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
return sstr.str();
} }
void handle_loops(RTLIL::Design *design) void handle_loops(RTLIL::Design *design)
@ -89,7 +87,7 @@ void handle_loops(RTLIL::Design *design)
// wires // wires
pool<RTLIL::Const> ids_seen; pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
auto it = cell->attributes.find("\\abc_scc_id"); auto it = cell->attributes.find(ID(abc_scc_id));
if (it != cell->attributes.end()) { if (it != cell->attributes.end()) {
auto r = ids_seen.insert(it->second); auto r = ids_seen.insert(it->second);
if (r.second) { if (r.second) {
@ -109,7 +107,7 @@ void handle_loops(RTLIL::Design *design)
log_assert(w->port_input); log_assert(w->port_input);
log_assert(b.offset < GetSize(w)); log_assert(b.offset < GetSize(w));
} }
w->set_bool_attribute("\\abc_scc_break"); w->set_bool_attribute(ID(abc_scc_break));
module->swap_names(b.wire, w); module->swap_names(b.wire, w);
c.second = RTLIL::SigBit(w, b.offset); c.second = RTLIL::SigBit(w, b.offset);
} }
@ -123,7 +121,7 @@ void handle_loops(RTLIL::Design *design)
std::vector<IdString> ports; std::vector<IdString> ports;
RTLIL::Module* box_module = design->module(cell->type); RTLIL::Module* box_module = design->module(cell->type);
if (box_module) { if (box_module) {
auto ports_csv = box_module->attributes.at("\\abc_scc_break", RTLIL::Const::from_string("")).decode_string(); auto ports_csv = box_module->attributes.at(ID(abc_scc_break), RTLIL::Const::from_string("")).decode_string();
for (const auto &port_name : split_tokens(ports_csv, ",")) { for (const auto &port_name : split_tokens(ports_csv, ",")) {
auto port_id = RTLIL::escape_id(port_name); auto port_id = RTLIL::escape_id(port_name);
auto kt = cell->connections_.find(port_id); auto kt = cell->connections_.find(port_id);
@ -142,7 +140,7 @@ void handle_loops(RTLIL::Design *design)
Wire *w = b.wire; Wire *w = b.wire;
if (!w) continue; if (!w) continue;
w->port_output = true; w->port_output = true;
w->set_bool_attribute("\\abc_scc_break"); w->set_bool_attribute(ID(abc_scc_break));
w = module->wire(stringf("%s.abci", w->name.c_str())); w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) { if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire)); w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
@ -446,14 +444,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (ifs.fail()) if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
log_assert(!design->module("$__abc9__")); log_assert(!design->module(ID($__abc9__)));
{ {
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
reader.parse_xaiger(); reader.parse_xaiger();
} }
ifs.close(); ifs.close();
Pass::call(design, stringf("write_verilog -noexpr -norename")); Pass::call(design, stringf("write_verilog -noexpr -norename"));
design->remove(design->module("$__abc9__")); design->remove(design->module(ID($__abc9__)));
#endif #endif
design->selection_stack.pop_back(); design->selection_stack.pop_back();
@ -462,7 +460,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// the expose operation -- remove them from PO/PI // the expose operation -- remove them from PO/PI
// and re-connecting them back together // and re-connecting them back together
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
auto it = wire->attributes.find("\\abc_scc_break"); auto it = wire->attributes.find(ID(abc_scc_break));
if (it != wire->attributes.end()) { if (it != wire->attributes.end()) {
wire->attributes.erase(it); wire->attributes.erase(it);
log_assert(wire->port_output); log_assert(wire->port_output);
@ -518,9 +516,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
log_assert(!design->module("$__abc9__")); log_assert(!design->module(ID($__abc9__)));
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
reader.parse_xaiger(box_lookup); reader.parse_xaiger(box_lookup);
ifs.close(); ifs.close();
@ -529,7 +527,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
#endif #endif
log_header(design, "Re-integrating ABC9 results.\n"); log_header(design, "Re-integrating ABC9 results.\n");
RTLIL::Module *mapped_mod = design->module("$__abc9__"); RTLIL::Module *mapped_mod = design->module(ID($__abc9__));
if (mapped_mod == NULL) if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `$__abc9__'.\n"); log_error("ABC output file does not contain a module `$__abc9__'.\n");
@ -537,7 +535,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
for (auto &it : mapped_mod->wires_) { for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second; RTLIL::Wire *w = it.second;
RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w)); RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx; if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
if (w->port_output) { if (w->port_output) {
RTLIL::Wire *wire = module->wire(w->name); RTLIL::Wire *wire = module->wire(w->name);
log_assert(wire); log_assert(wire);
@ -559,14 +557,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
vector<RTLIL::Cell*> boxes; vector<RTLIL::Cell*> boxes;
for (const auto &it : module->cells_) { for (const auto &it : module->cells_) {
auto cell = it.second; auto cell = it.second;
if (cell->type.in("$_AND_", "$_NOT_")) { if (cell->type.in(ID($_AND_), ID($_NOT_))) {
module->remove(cell); module->remove(cell);
continue; continue;
} }
auto jt = abc_box.find(cell->type); auto jt = abc_box.find(cell->type);
if (jt == abc_box.end()) { if (jt == abc_box.end()) {
RTLIL::Module* box_module = design->module(cell->type); RTLIL::Module* box_module = design->module(cell->type);
jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count("\\abc_box_id"))).first; jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
} }
if (jt->second) if (jt->second)
boxes.emplace_back(cell); boxes.emplace_back(cell);
@ -577,20 +575,20 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers; dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks; dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
std::map<std::string, int> cell_stats; std::map<IdString, int> cell_stats;
for (auto c : mapped_mod->cells()) for (auto c : mapped_mod->cells())
{ {
toposort.node(c->name); toposort.node(c->name);
RTLIL::Cell *cell = nullptr; RTLIL::Cell *cell = nullptr;
if (c->type == "$_NOT_") { if (c->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = c->getPort("\\A"); RTLIL::SigBit a_bit = c->getPort(ID(A));
RTLIL::SigBit y_bit = c->getPort("\\Y"); RTLIL::SigBit y_bit = c->getPort(ID(Y));
bit_users[a_bit].insert(c->name); bit_users[a_bit].insert(c->name);
bit_drivers[y_bit].insert(c->name); bit_drivers[y_bit].insert(c->name);
if (!a_bit.wire) { if (!a_bit.wire) {
c->setPort("\\Y", module->addWire(NEW_ID)); c->setPort(ID(Y), module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire); log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -618,8 +616,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01")); RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort("\\A")].push_back(cell); bit2sinks[cell->getPort(ID(A))].push_back(cell);
cell_stats["$lut"]++; cell_stats[ID($lut)]++;
} }
else else
not2drivers[c] = driver_lut; not2drivers[c] = driver_lut;
@ -627,18 +625,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
} }
else else
log_abort(); log_abort();
if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
continue; continue;
} }
cell_stats[RTLIL::unescape_id(c->type)]++; cell_stats[RTLIL::unescape_id(c->type)]++;
RTLIL::Cell *existing_cell = nullptr; RTLIL::Cell *existing_cell = nullptr;
if (c->type == "$lut") { if (c->type == ID($lut)) {
if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT") == RTLIL::Const::from_string("01")) { if (GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(c->getPort("\\A").as_wire()->name)); SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID(A)).as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(c->getPort("\\Y").as_wire()->name)); SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID(Y)).as_wire()->name));
module->connect(my_y, my_a); module->connect(my_y, my_a);
if (markgroups) c->attributes["\\abcgroup"] = map_autoidx; if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
log_abort(); log_abort();
continue; continue;
} }
@ -651,7 +649,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
module->swap_names(cell, existing_cell); module->swap_names(cell, existing_cell);
} }
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (existing_cell) { if (existing_cell) {
cell->parameters = existing_cell->parameters; cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes; cell->attributes = existing_cell->attributes;
@ -747,14 +745,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) { for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
RTLIL::Cell *not_cell = mapped_mod->cell(*ii); RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
log_assert(not_cell); log_assert(not_cell);
if (not_cell->type != "$_NOT_") if (not_cell->type != ID($_NOT_))
continue; continue;
auto it = not2drivers.find(not_cell); auto it = not2drivers.find(not_cell);
if (it == not2drivers.end()) if (it == not2drivers.end())
continue; continue;
RTLIL::Cell *driver_lut = it->second; RTLIL::Cell *driver_lut = it->second;
RTLIL::SigBit a_bit = not_cell->getPort("\\A"); RTLIL::SigBit a_bit = not_cell->getPort(ID(A));
RTLIL::SigBit y_bit = not_cell->getPort("\\Y"); RTLIL::SigBit y_bit = not_cell->getPort(ID(Y));
RTLIL::Const driver_mask; RTLIL::Const driver_mask;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name)); a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
@ -765,13 +763,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
goto clone_lut; goto clone_lut;
for (auto sink_cell : jt->second) for (auto sink_cell : jt->second)
if (sink_cell->type != "$lut") if (sink_cell->type != ID($lut))
goto clone_lut; goto clone_lut;
// Push downstream LUTs past inverter // Push downstream LUTs past inverter
for (auto sink_cell : jt->second) { for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort("\\A"); SigSpec A = sink_cell->getPort(ID(A));
RTLIL::Const mask = sink_cell->getParam("\\LUT"); RTLIL::Const mask = sink_cell->getParam(ID(LUT));
int index = 0; int index = 0;
for (; index < GetSize(A); index++) for (; index < GetSize(A); index++)
if (A[index] == a_bit) if (A[index] == a_bit)
@ -784,8 +782,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
i += 1 << (index+1); i += 1 << (index+1);
} }
A[index] = y_bit; A[index] = y_bit;
sink_cell->setPort("\\A", A); sink_cell->setPort(ID(A), A);
sink_cell->setParam("\\LUT", mask); sink_cell->setParam(ID(LUT), mask);
} }
// Since we have rewritten all sinks (which we know // Since we have rewritten all sinks (which we know
@ -794,16 +792,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// that the original driving LUT will become dangling // that the original driving LUT will become dangling
// and get cleaned away // and get cleaned away
clone_lut: clone_lut:
driver_mask = driver_lut->getParam("\\LUT"); driver_mask = driver_lut->getParam(ID(LUT));
for (auto &b : driver_mask.bits) { for (auto &b : driver_mask.bits) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1; if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0; else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
} }
auto cell = module->addLut(NEW_ID, auto cell = module->addLut(NEW_ID,
driver_lut->getPort("\\A"), driver_lut->getPort(ID(A)),
y_bit, y_bit,
driver_mask); driver_mask);
for (auto &bit : cell->connections_.at("\\A")) { for (auto &bit : cell->connections_.at(ID(A))) {
bit.wire = module->wires_.at(remap_name(bit.wire->name)); bit.wire = module->wires_.at(remap_name(bit.wire->name));
bit2sinks[bit].push_back(cell); bit2sinks[bit].push_back(cell);
} }
@ -1084,7 +1082,7 @@ struct Abc9Pass : public Pass {
dict<int,IdString> box_lookup; dict<int,IdString> box_lookup;
for (auto m : design->modules()) { for (auto m : design->modules()) {
auto it = m->attributes.find("\\abc_box_id"); auto it = m->attributes.find(ID(abc_box_id));
if (it == m->attributes.end()) if (it == m->attributes.end())
continue; continue;
if (m->name.begins_with("$paramod")) if (m->name.begins_with("$paramod"))
@ -1099,7 +1097,7 @@ struct Abc9Pass : public Pass {
for (auto mod : design->selected_modules()) for (auto mod : design->selected_modules())
{ {
if (mod->attributes.count("\\abc_box_id")) if (mod->attributes.count(ID(abc_box_id)))
continue; continue;
if (mod->processes.size() > 0) { if (mod->processes.size() > 0) {
@ -1153,16 +1151,16 @@ struct Abc9Pass : public Pass {
} }
} }
if (cell->type.in("$_DFF_N_", "$_DFF_P_")) if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{ {
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
} }
else else
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_")) if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{ {
bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"); bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"); bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
} }
else else
continue; continue;

4
passes/techmap/aigmap.cc
View File

@ -66,10 +66,10 @@ struct AigmapPass : public Pass {
{ {
Aig aig(cell); Aig aig(cell);
if (cell->type.in("$_AND_", "$_NOT_")) if (cell->type.in(ID($_AND_), ID($_NOT_)))
aig.name.clear(); aig.name.clear();
if (nand_mode && cell->type == "$_NAND_") if (nand_mode && cell->type == ID($_NAND_))
aig.name.clear(); aig.name.clear();
if (aig.name.empty()) { if (aig.name.empty()) {

86
passes/techmap/alumacc.cc
View File

@ -61,7 +61,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_eq() { RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0) if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->get_src_attribute()); cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID(X)), false, alu_cell->get_src_attribute());
return cached_eq; return cached_eq;
} }
@ -73,7 +73,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_cf() { RTLIL::SigSpec get_cf() {
if (GetSize(cached_cf) == 0) { if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort("\\CO"); cached_cf = alu_cell->getPort(ID(CO));
log_assert(GetSize(cached_cf) >= 1); log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute()); cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
} }
@ -82,7 +82,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_of() { RTLIL::SigSpec get_of() {
if (GetSize(cached_of) == 0) { if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort("\\CO"), alu_cell->getPort("\\CI")}; cached_of = {alu_cell->getPort(ID(CO)), alu_cell->getPort(ID(CI))};
log_assert(GetSize(cached_of) >= 2); log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
} }
@ -91,7 +91,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_sf() { RTLIL::SigSpec get_sf() {
if (GetSize(cached_sf) == 0) { if (GetSize(cached_sf) == 0) {
cached_sf = alu_cell->getPort("\\Y"); cached_sf = alu_cell->getPort(ID(Y));
cached_sf = cached_sf[GetSize(cached_sf)-1]; cached_sf = cached_sf[GetSize(cached_sf)-1];
} }
return cached_sf; return cached_sf;
@ -125,7 +125,7 @@ struct AlumaccWorker
{ {
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (!cell->type.in("$pos", "$neg", "$add", "$sub", "$mul")) if (!cell->type.in(ID($pos), ID($neg), ID($add), ID($sub), ID($mul)))
continue; continue;
log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type)); log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type));
@ -134,38 +134,38 @@ struct AlumaccWorker
Macc::port_t new_port; Macc::port_t new_port;
n->cell = cell; n->cell = cell;
n->y = sigmap(cell->getPort("\\Y")); n->y = sigmap(cell->getPort(ID(Y)));
n->users = 0; n->users = 0;
for (auto bit : n->y) for (auto bit : n->y)
n->users = max(n->users, bit_users.at(bit) - 1); n->users = max(n->users, bit_users.at(bit) - 1);
if (cell->type.in("$pos", "$neg")) if (cell->type.in(ID($pos), ID($neg)))
{ {
new_port.in_a = sigmap(cell->getPort("\\A")); new_port.in_a = sigmap(cell->getPort(ID(A)));
new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool(); new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.do_subtract = cell->type == "$neg"; new_port.do_subtract = cell->type == ID($neg);
n->macc.ports.push_back(new_port); n->macc.ports.push_back(new_port);
} }
if (cell->type.in("$add", "$sub")) if (cell->type.in(ID($add), ID($sub)))
{ {
new_port.in_a = sigmap(cell->getPort("\\A")); new_port.in_a = sigmap(cell->getPort(ID(A)));
new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool(); new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.do_subtract = false; new_port.do_subtract = false;
n->macc.ports.push_back(new_port); n->macc.ports.push_back(new_port);
new_port.in_a = sigmap(cell->getPort("\\B")); new_port.in_a = sigmap(cell->getPort(ID(B)));
new_port.is_signed = cell->getParam("\\B_SIGNED").as_bool(); new_port.is_signed = cell->getParam(ID(B_SIGNED)).as_bool();
new_port.do_subtract = cell->type == "$sub"; new_port.do_subtract = cell->type == ID($sub);
n->macc.ports.push_back(new_port); n->macc.ports.push_back(new_port);
} }
if (cell->type.in("$mul")) if (cell->type.in(ID($mul)))
{ {
new_port.in_a = sigmap(cell->getPort("\\A")); new_port.in_a = sigmap(cell->getPort(ID(A)));
new_port.in_b = sigmap(cell->getPort("\\B")); new_port.in_b = sigmap(cell->getPort(ID(B)));
new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool(); new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.do_subtract = false; new_port.do_subtract = false;
n->macc.ports.push_back(new_port); n->macc.ports.push_back(new_port);
} }
@ -351,7 +351,7 @@ struct AlumaccWorker
for (auto &it : sig_macc) for (auto &it : sig_macc)
{ {
auto n = it.second; auto n = it.second;
auto cell = module->addCell(NEW_ID, "$macc"); auto cell = module->addCell(NEW_ID, ID($macc));
macc_counter++; macc_counter++;
@ -361,7 +361,7 @@ struct AlumaccWorker
n->macc.optimize(GetSize(n->y)); n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell); n->macc.to_cell(cell);
cell->setPort("\\Y", n->y); cell->setPort(ID(Y), n->y);
cell->fixup_parameters(); cell->fixup_parameters();
module->remove(n->cell); module->remove(n->cell);
delete n; delete n;
@ -376,9 +376,9 @@ struct AlumaccWorker
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type.in("$lt", "$le", "$ge", "$gt")) if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt)))
lge_cells.push_back(cell); lge_cells.push_back(cell);
if (cell->type.in("$eq", "$eqx", "$ne", "$nex")) if (cell->type.in(ID($eq), ID($eqx), ID($ne), ID($nex)))
eq_cells.push_back(cell); eq_cells.push_back(cell);
} }
@ -386,13 +386,13 @@ struct AlumaccWorker
{ {
log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type)); log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
bool cmp_less = cell->type.in("$lt", "$le"); bool cmp_less = cell->type.in(ID($lt), ID($le));
bool cmp_equal = cell->type.in("$le", "$ge"); bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort("\\A")); RTLIL::SigSpec A = sigmap(cell->getPort(ID(A)));
RTLIL::SigSpec B = sigmap(cell->getPort("\\B")); RTLIL::SigSpec B = sigmap(cell->getPort(ID(B)));
RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y")); RTLIL::SigSpec Y = sigmap(cell->getPort(ID(Y)));
if (B < A && GetSize(B)) { if (B < A && GetSize(B)) {
cmp_less = !cmp_less; cmp_less = !cmp_less;
@ -427,12 +427,12 @@ struct AlumaccWorker
for (auto cell : eq_cells) for (auto cell : eq_cells)
{ {
bool cmp_equal = cell->type.in("$eq", "$eqx"); bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort("\\A")); RTLIL::SigSpec A = sigmap(cell->getPort(ID(A)));
RTLIL::SigSpec B = sigmap(cell->getPort("\\B")); RTLIL::SigSpec B = sigmap(cell->getPort(ID(B)));
RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y")); RTLIL::SigSpec Y = sigmap(cell->getPort(ID(Y)));
if (B < A && GetSize(B)) if (B < A && GetSize(B))
std::swap(A, B); std::swap(A, B);
@ -471,7 +471,7 @@ struct AlumaccWorker
goto delete_node; goto delete_node;
} }
n->alu_cell = module->addCell(NEW_ID, "$alu"); n->alu_cell = module->addCell(NEW_ID, ID($alu));
alu_counter++; alu_counter++;
log(" creating $alu cell for "); log(" creating $alu cell for ");
@ -482,13 +482,13 @@ struct AlumaccWorker
if (n->cells.size() > 0) if (n->cells.size() > 0)
n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute()); n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
n->alu_cell->setPort("\\A", n->a); n->alu_cell->setPort(ID(A), n->a);
n->alu_cell->setPort("\\B", n->b); n->alu_cell->setPort(ID(B), n->b);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : State::S0); n->alu_cell->setPort(ID(CI), GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? State::S1 : State::S0); n->alu_cell->setPort(ID(BI), n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort("\\Y", n->y); n->alu_cell->setPort(ID(Y), n->y);
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y))); n->alu_cell->setPort(ID(X), module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y))); n->alu_cell->setPort(ID(CO), module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed); n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp) for (auto &it : n->cmp)

6
passes/techmap/deminout.cc
View File

@ -83,13 +83,13 @@ struct DeminoutPass : public Pass {
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
bits_used.insert(bit); bits_used.insert(bit);
if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf")) if (conn.first == ID(Y) && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
{ {
bool tribuf = cell->type.in("$_TBUF_", "$tribuf"); bool tribuf = cell->type.in(ID($_TBUF_), ID($tribuf));
if (!tribuf) { if (!tribuf) {
for (auto &c : cell->connections()) { for (auto &c : cell->connections()) {
if (!c.first.in("\\A", "\\B")) if (!c.first.in(ID(A), ID(B)))
continue; continue;
for (auto b : sigmap(c.second)) for (auto b : sigmap(c.second))
if (b == State::Sz) if (b == State::Sz)

104
passes/techmap/dff2dffe.cc
View File

@ -52,13 +52,13 @@ struct Dff2dffeWorker
} }
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type.in("$mux", "$pmux", "$_MUX_")) { if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID(Y)));
for (int i = 0; i < GetSize(sig_y); i++) for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i); bit2mux[sig_y[i]] = cell_int_t(cell, i);
} }
if (direct_dict.empty()) { if (direct_dict.empty()) {
if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_")) if (cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_)))
dff_cells.push_back(cell); dff_cells.push_back(cell);
} else { } else {
if (direct_dict.count(cell->type)) if (direct_dict.count(cell->type))
@ -86,9 +86,9 @@ struct Dff2dffeWorker
return ret; return ret;
cell_int_t mux_cell_int = bit2mux.at(d); cell_int_t mux_cell_int = bit2mux.at(d);
RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort("\\A")); RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID(A)));
RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort("\\B")); RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID(B)));
RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort("\\S")); RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID(S)));
int width = GetSize(sig_a), index = mux_cell_int.second; int width = GetSize(sig_a), index = mux_cell_int.second;
for (int i = 0; i < GetSize(sig_s); i++) for (int i = 0; i < GetSize(sig_s); i++)
@ -97,9 +97,9 @@ struct Dff2dffeWorker
ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path); ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
if (sig_b[i*width + index] == q) { if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B"); RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(B));
s[i*width + index] = RTLIL::Sx; s[i*width + index] = RTLIL::Sx;
mux_cell_int.first->setPort("\\B", s); mux_cell_int.first->setPort(ID(B), s);
} }
return ret; return ret;
@ -120,9 +120,9 @@ struct Dff2dffeWorker
ret.insert(pat); ret.insert(pat);
if (sig_b[i*width + index] == q) { if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B"); RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(B));
s[i*width + index] = RTLIL::Sx; s[i*width + index] = RTLIL::Sx;
mux_cell_int.first->setPort("\\B", s); mux_cell_int.first->setPort(ID(B), s);
} }
} }
@ -130,9 +130,9 @@ struct Dff2dffeWorker
ret.insert(pat); ret.insert(pat);
if (sig_a[index] == q) { if (sig_a[index] == q) {
RTLIL::SigSpec s = mux_cell_int.first->getPort("\\A"); RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(A));
s[index] = RTLIL::Sx; s[index] = RTLIL::Sx;
mux_cell_int.first->setPort("\\A", s); mux_cell_int.first->setPort(ID(A), s);
} }
return ret; return ret;
@ -185,8 +185,8 @@ struct Dff2dffeWorker
void handle_dff_cell(RTLIL::Cell *dff_cell) void handle_dff_cell(RTLIL::Cell *dff_cell)
{ {
RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort("\\D")); RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID(D)));
RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort("\\Q")); RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID(Q)));
std::map<patterns_t, std::set<int>> grouped_patterns; std::map<patterns_t, std::set<int>> grouped_patterns;
std::set<int> remaining_indices; std::set<int> remaining_indices;
@ -208,16 +208,16 @@ struct Dff2dffeWorker
} }
if (!direct_dict.empty()) { if (!direct_dict.empty()) {
log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q)); log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q));
dff_cell->setPort("\\E", make_patterns_logic(it.first, true)); dff_cell->setPort(ID(E), make_patterns_logic(it.first, true));
dff_cell->type = direct_dict.at(dff_cell->type); dff_cell->type = direct_dict.at(dff_cell->type);
} else } else
if (dff_cell->type == "$dff") { if (dff_cell->type == ID($dff)) {
RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort("\\CLK"), make_patterns_logic(it.first, false), RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID(CLK)), make_patterns_logic(it.first, false),
new_sig_d, new_sig_q, dff_cell->getParam("\\CLK_POLARITY").as_bool(), true); new_sig_d, new_sig_q, dff_cell->getParam(ID(CLK_POLARITY)).as_bool(), true);
log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
} else { } else {
RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort("\\C"), make_patterns_logic(it.first, true), RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID(C)), make_patterns_logic(it.first, true),
new_sig_d, new_sig_q, dff_cell->type == "$_DFF_P_", true); new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true);
log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
} }
} }
@ -235,9 +235,9 @@ struct Dff2dffeWorker
new_sig_d.append(sig_d[i]); new_sig_d.append(sig_d[i]);
new_sig_q.append(sig_q[i]); new_sig_q.append(sig_q[i]);
} }
dff_cell->setPort("\\D", new_sig_d); dff_cell->setPort(ID(D), new_sig_d);
dff_cell->setPort("\\Q", new_sig_q); dff_cell->setPort(ID(Q), new_sig_q);
dff_cell->setParam("\\WIDTH", GetSize(remaining_indices)); dff_cell->setParam(ID(WIDTH), GetSize(remaining_indices));
} }
} }
@ -316,25 +316,25 @@ struct Dff2dffePass : public Pass {
if (args[argidx] == "-direct-match" && argidx + 1 < args.size()) { if (args[argidx] == "-direct-match" && argidx + 1 < args.size()) {
bool found_match = false; bool found_match = false;
const char *pattern = args[++argidx].c_str(); const char *pattern = args[++argidx].c_str();
if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict["$_DFF_P_" ] = "$_DFFE_PP_"; if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict[ID($_DFF_P_) ] = ID($_DFFE_PP_);
if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict["$_DFF_N_" ] = "$_DFFE_NP_"; if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict[ID($_DFF_N_) ] = ID($_DFFE_NP_);
if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict["$_DFF_NN0_"] = "$__DFFE_NN0"; if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($__DFFE_NN0);
if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict["$_DFF_NN1_"] = "$__DFFE_NN1"; if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($__DFFE_NN1);
if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict["$_DFF_NP0_"] = "$__DFFE_NP0"; if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($__DFFE_NP0);
if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict["$_DFF_NP1_"] = "$__DFFE_NP1"; if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($__DFFE_NP1);
if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict["$_DFF_PN0_"] = "$__DFFE_PN0"; if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($__DFFE_PN0);
if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict["$_DFF_PN1_"] = "$__DFFE_PN1"; if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($__DFFE_PN1);
if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict["$_DFF_PP0_"] = "$__DFFE_PP0"; if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($__DFFE_PP0);
if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict["$_DFF_PP1_"] = "$__DFFE_PP1"; if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($__DFFE_PP1);
if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict["$__DFFS_NN0_"] = "$__DFFSE_NN0"; if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict[ID($__DFFS_NN0_)] = ID($__DFFSE_NN0);
if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict["$__DFFS_NN1_"] = "$__DFFSE_NN1"; if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict[ID($__DFFS_NN1_)] = ID($__DFFSE_NN1);
if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict["$__DFFS_NP0_"] = "$__DFFSE_NP0"; if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict[ID($__DFFS_NP0_)] = ID($__DFFSE_NP0);
if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict["$__DFFS_NP1_"] = "$__DFFSE_NP1"; if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict[ID($__DFFS_NP1_)] = ID($__DFFSE_NP1);
if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict["$__DFFS_PN0_"] = "$__DFFSE_PN0"; if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict[ID($__DFFS_PN0_)] = ID($__DFFSE_PN0);
if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict["$__DFFS_PN1_"] = "$__DFFSE_PN1"; if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict[ID($__DFFS_PN1_)] = ID($__DFFSE_PN1);
if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict["$__DFFS_PP0_"] = "$__DFFSE_PP0"; if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict[ID($__DFFS_PP0_)] = ID($__DFFSE_PP0);
if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict["$__DFFS_PP1_"] = "$__DFFSE_PP1"; if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict[ID($__DFFS_PP1_)] = ID($__DFFSE_PP1);
if (!found_match) if (!found_match)
log_cmd_error("No cell types matched pattern '%s'.\n", pattern); log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
continue; continue;
@ -355,25 +355,25 @@ struct Dff2dffePass : public Pass {
if (unmap_mode) { if (unmap_mode) {
SigMap sigmap(mod); SigMap sigmap(mod);
for (auto cell : mod->selected_cells()) { for (auto cell : mod->selected_cells()) {
if (cell->type == "$dffe") { if (cell->type == ID($dffe)) {
if (min_ce_use >= 0) { if (min_ce_use >= 0) {
int ce_use = 0; int ce_use = 0;
for (auto cell_other : mod->selected_cells()) { for (auto cell_other : mod->selected_cells()) {
if (cell_other->type != cell->type) if (cell_other->type != cell->type)
continue; continue;
if (sigmap(cell->getPort("\\EN")) == sigmap(cell_other->getPort("\\EN"))) if (sigmap(cell->getPort(ID(EN))) == sigmap(cell_other->getPort(ID(EN))))
ce_use++; ce_use++;
} }
if (ce_use >= min_ce_use) if (ce_use >= min_ce_use)
continue; continue;
} }
RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort("\\D"))); RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID(D))));
mod->addDff(NEW_ID, cell->getPort("\\CLK"), tmp, cell->getPort("\\Q"), cell->getParam("\\CLK_POLARITY").as_bool()); mod->addDff(NEW_ID, cell->getPort(ID(CLK)), tmp, cell->getPort(ID(Q)), cell->getParam(ID(CLK_POLARITY)).as_bool());
if (cell->getParam("\\EN_POLARITY").as_bool()) if (cell->getParam(ID(EN_POLARITY)).as_bool())
mod->addMux(NEW_ID, cell->getPort("\\Q"), cell->getPort("\\D"), cell->getPort("\\EN"), tmp); mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(EN)), tmp);
else else
mod->addMux(NEW_ID, cell->getPort("\\D"), cell->getPort("\\Q"), cell->getPort("\\EN"), tmp); mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(EN)), tmp);
mod->remove(cell); mod->remove(cell);
continue; continue;
} }
@ -383,7 +383,7 @@ struct Dff2dffePass : public Pass {
for (auto cell_other : mod->selected_cells()) { for (auto cell_other : mod->selected_cells()) {
if (cell_other->type != cell->type) if (cell_other->type != cell->type)
continue; continue;
if (sigmap(cell->getPort("\\E")) == sigmap(cell_other->getPort("\\E"))) if (sigmap(cell->getPort(ID(E))) == sigmap(cell_other->getPort(ID(E))))
ce_use++; ce_use++;
} }
if (ce_use >= min_ce_use) if (ce_use >= min_ce_use)
@ -393,11 +393,11 @@ struct Dff2dffePass : public Pass {
bool clk_pol = cell->type.compare(7, 1, "P") == 0; bool clk_pol = cell->type.compare(7, 1, "P") == 0;
bool en_pol = cell->type.compare(8, 1, "P") == 0; bool en_pol = cell->type.compare(8, 1, "P") == 0;
RTLIL::SigSpec tmp = mod->addWire(NEW_ID); RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol); mod->addDff(NEW_ID, cell->getPort(ID(C)), tmp, cell->getPort(ID(Q)), clk_pol);
if (en_pol) if (en_pol)
mod->addMux(NEW_ID, cell->getPort("\\Q"), cell->getPort("\\D"), cell->getPort("\\E"), tmp); mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(E)), tmp);
else else
mod->addMux(NEW_ID, cell->getPort("\\D"), cell->getPort("\\Q"), cell->getPort("\\E"), tmp); mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(E)), tmp);
mod->remove(cell); mod->remove(cell);
continue; continue;
} }

48
passes/techmap/dff2dffs.cc
View File

@ -51,8 +51,8 @@ struct Dff2dffsPass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
pool<IdString> dff_types; pool<IdString> dff_types;
dff_types.insert("$_DFF_N_"); dff_types.insert(ID($_DFF_N_));
dff_types.insert("$_DFF_P_"); dff_types.insert(ID($_DFF_P_));
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
@ -69,19 +69,19 @@ struct Dff2dffsPass : public Pass {
continue; continue;
} }
if (cell->type != "$_MUX_") if (cell->type != ID($_MUX_))
continue; continue;
SigBit bit_a = sigmap(cell->getPort("\\A")); SigBit bit_a = sigmap(cell->getPort(ID(A)));
SigBit bit_b = sigmap(cell->getPort("\\B")); SigBit bit_b = sigmap(cell->getPort(ID(B)));
if (bit_a.wire == nullptr || bit_b.wire == nullptr) if (bit_a.wire == nullptr || bit_b.wire == nullptr)
sr_muxes[sigmap(cell->getPort("\\Y"))] = cell; sr_muxes[sigmap(cell->getPort(ID(Y)))] = cell;
} }
for (auto cell : ff_cells) for (auto cell : ff_cells)
{ {
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID(D));
if (GetSize(sig_d) < 1) if (GetSize(sig_d) < 1)
continue; continue;
@ -92,9 +92,9 @@ struct Dff2dffsPass : public Pass {
continue; continue;
Cell *mux_cell = sr_muxes.at(bit_d); Cell *mux_cell = sr_muxes.at(bit_d);
SigBit bit_a = sigmap(mux_cell->getPort("\\A")); SigBit bit_a = sigmap(mux_cell->getPort(ID(A)));
SigBit bit_b = sigmap(mux_cell->getPort("\\B")); SigBit bit_b = sigmap(mux_cell->getPort(ID(B)));
SigBit bit_s = sigmap(mux_cell->getPort("\\S")); SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
@ -114,26 +114,26 @@ struct Dff2dffsPass : public Pass {
} }
if (sr_val == State::S1) { if (sr_val == State::S1) {
if (cell->type == "$_DFF_N_") { if (cell->type == ID($_DFF_N_)) {
if (invert_sr) cell->type = "$__DFFS_NN1_"; if (invert_sr) cell->type = ID($__DFFS_NN1_);
else cell->type = "$__DFFS_NP1_"; else cell->type = ID($__DFFS_NP1_);
} else { } else {
log_assert(cell->type == "$_DFF_P_"); log_assert(cell->type == ID($_DFF_P_));
if (invert_sr) cell->type = "$__DFFS_PN1_"; if (invert_sr) cell->type = ID($__DFFS_PN1_);
else cell->type = "$__DFFS_PP1_"; else cell->type = ID($__DFFS_PP1_);
} }
} else { } else {
if (cell->type == "$_DFF_N_") { if (cell->type == ID($_DFF_N_)) {
if (invert_sr) cell->type = "$__DFFS_NN0_"; if (invert_sr) cell->type = ID($__DFFS_NN0_);
else cell->type = "$__DFFS_NP0_"; else cell->type = ID($__DFFS_NP0_);
} else { } else {
log_assert(cell->type == "$_DFF_P_"); log_assert(cell->type == ID($_DFF_P_));
if (invert_sr) cell->type = "$__DFFS_PN0_"; if (invert_sr) cell->type = ID($__DFFS_PN0_);
else cell->type = "$__DFFS_PP0_"; else cell->type = ID($__DFFS_PP0_);
} }
} }
cell->setPort("\\R", sr_sig); cell->setPort(ID(R), sr_sig);
cell->setPort("\\D", bit_d); cell->setPort(ID(D), bit_d);
} }
} }
} }

10
passes/techmap/dffinit.cc
View File

@ -99,8 +99,8 @@ struct DffinitPass : public Pass {
pool<SigBit> used_bits; pool<SigBit> used_bits;
for (auto wire : module->selected_wires()) { for (auto wire : module->selected_wires()) {
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID(init))) {
Const value = wire->attributes.at("\\init"); Const value = wire->attributes.at(ID(init));
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
if (value[i] != State::Sx) if (value[i] != State::Sx)
init_bits[sigmap(SigBit(wire, i))] = value[i]; init_bits[sigmap(SigBit(wire, i))] = value[i];
@ -161,8 +161,8 @@ struct DffinitPass : public Pass {
} }
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID(init))) {
Const &value = wire->attributes.at("\\init"); Const &value = wire->attributes.at(ID(init));
bool do_cleanup = true; bool do_cleanup = true;
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i)); SigBit bit = sigmap(SigBit(wire, i));
@ -173,7 +173,7 @@ struct DffinitPass : public Pass {
} }
if (do_cleanup) { if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
wire->attributes.erase("\\init"); wire->attributes.erase(ID(init));
} }
} }
} }

142
passes/techmap/dfflibmap.cc
View File

@ -27,12 +27,12 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct cell_mapping { struct cell_mapping {
std::string cell_name; IdString cell_name;
std::map<std::string, char> ports; std::map<IdString, char> ports;
}; };
static std::map<RTLIL::IdString, cell_mapping> cell_mappings; static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
static void logmap(std::string dff) static void logmap(IdString dff)
{ {
if (cell_mappings.count(dff) == 0) { if (cell_mappings.count(dff) == 0) {
log(" unmapped dff cell: %s\n", dff.c_str()); log(" unmapped dff cell: %s\n", dff.c_str());
@ -54,26 +54,26 @@ static void logmap(std::string dff)
static void logmap_all() static void logmap_all()
{ {
logmap("$_DFF_N_"); logmap(ID($_DFF_N_));
logmap("$_DFF_P_"); logmap(ID($_DFF_P_));
logmap("$_DFF_NN0_"); logmap(ID($_DFF_NN0_));
logmap("$_DFF_NN1_"); logmap(ID($_DFF_NN1_));
logmap("$_DFF_NP0_"); logmap(ID($_DFF_NP0_));
logmap("$_DFF_NP1_"); logmap(ID($_DFF_NP1_));
logmap("$_DFF_PN0_"); logmap(ID($_DFF_PN0_));
logmap("$_DFF_PN1_"); logmap(ID($_DFF_PN1_));
logmap("$_DFF_PP0_"); logmap(ID($_DFF_PP0_));
logmap("$_DFF_PP1_"); logmap(ID($_DFF_PP1_));
logmap("$_DFFSR_NNN_"); logmap(ID($_DFFSR_NNN_));
logmap("$_DFFSR_NNP_"); logmap(ID($_DFFSR_NNP_));
logmap("$_DFFSR_NPN_"); logmap(ID($_DFFSR_NPN_));
logmap("$_DFFSR_NPP_"); logmap(ID($_DFFSR_NPP_));
logmap("$_DFFSR_PNN_"); logmap(ID($_DFFSR_PNN_));
logmap("$_DFFSR_PNP_"); logmap(ID($_DFFSR_PNP_));
logmap("$_DFFSR_PPN_"); logmap(ID($_DFFSR_PPN_));
logmap("$_DFFSR_PPP_"); logmap(ID($_DFFSR_PPP_));
} }
static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol) static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol)
@ -115,10 +115,10 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name,
return false; return false;
} }
static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode) static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode)
{ {
LibertyAst *best_cell = NULL; LibertyAst *best_cell = NULL;
std::map<std::string, char> best_cell_ports; std::map<IdString, char> best_cell_ports;
int best_cell_pins = 0; int best_cell_pins = 0;
bool best_cell_noninv = false; bool best_cell_noninv = false;
double best_cell_area = 0; double best_cell_area = 0;
@ -155,7 +155,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
continue; continue;
} }
std::map<std::string, char> this_cell_ports; std::map<IdString, char> this_cell_ports;
this_cell_ports[cell_clk_pin] = 'C'; this_cell_ports[cell_clk_pin] = 'C';
if (has_reset) if (has_reset)
this_cell_ports[cell_rst_pin] = 'R'; this_cell_ports[cell_rst_pin] = 'R';
@ -236,10 +236,10 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
} }
} }
static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode) static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode)
{ {
LibertyAst *best_cell = NULL; LibertyAst *best_cell = NULL;
std::map<std::string, char> best_cell_ports; std::map<IdString, char> best_cell_ports;
int best_cell_pins = 0; int best_cell_pins = 0;
bool best_cell_noninv = false; bool best_cell_noninv = false;
double best_cell_area = 0; double best_cell_area = 0;
@ -272,7 +272,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol) if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
continue; continue;
std::map<std::string, char> this_cell_ports; std::map<IdString, char> this_cell_ports;
this_cell_ports[cell_clk_pin] = 'C'; this_cell_ports[cell_clk_pin] = 'C';
this_cell_ports[cell_set_pin] = 'S'; this_cell_ports[cell_set_pin] = 'S';
this_cell_ports[cell_clr_pin] = 'R'; this_cell_ports[cell_clr_pin] = 'R';
@ -404,7 +404,7 @@ static bool expand_cellmap(std::string pattern, std::string inv)
return return_status; return return_status;
} }
static void map_sr_to_arst(const char *from, const char *to) static void map_sr_to_arst(IdString from, IdString to)
{ {
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0) if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return; return;
@ -419,7 +419,7 @@ static void map_sr_to_arst(const char *from, const char *to)
log_assert(from_clk_pol == to_clk_pol); log_assert(from_clk_pol == to_clk_pol);
log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol); log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
log(" create mapping for %s from mapping for %s.\n", to, from); log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
cell_mappings[to].cell_name = cell_mappings[from].cell_name; cell_mappings[to].cell_name = cell_mappings[from].cell_name;
cell_mappings[to].ports = cell_mappings[from].ports; cell_mappings[to].ports = cell_mappings[from].ports;
@ -450,7 +450,7 @@ static void map_sr_to_arst(const char *from, const char *to)
} }
} }
static void map_adff_to_dff(const char *from, const char *to) static void map_adff_to_dff(IdString from, IdString to)
{ {
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0) if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return; return;
@ -461,7 +461,7 @@ static void map_adff_to_dff(const char *from, const char *to)
log_assert(from_clk_pol == to_clk_pol); log_assert(from_clk_pol == to_clk_pol);
log(" create mapping for %s from mapping for %s.\n", to, from); log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
cell_mappings[to].cell_name = cell_mappings[from].cell_name; cell_mappings[to].cell_name = cell_mappings[from].cell_name;
cell_mappings[to].ports = cell_mappings[from].ports; cell_mappings[to].ports = cell_mappings[from].ports;
@ -484,8 +484,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second); cell_list.push_back(it.second);
if (it.second->type == "$_NOT_") if (it.second->type == ID($_NOT_))
notmap[sigmap(it.second->getPort("\\A"))].insert(it.second); notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second);
} }
std::map<std::string, int> stats; std::map<std::string, int> stats;
@ -499,7 +499,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
module->remove(cell); module->remove(cell);
cell_mapping &cm = cell_mappings[cell_type]; cell_mapping &cm = cell_mappings[cell_type];
RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name); RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name.str());
new_cell->set_src_attribute(src); new_cell->set_src_attribute(src);
@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
sig = module->addWire(NEW_ID, GetSize(old_sig)); sig = module->addWire(NEW_ID, GetSize(old_sig));
if (has_q && has_qn) { if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) { for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort("\\Y"), sig); module->connect(it->getPort(ID(Y)), sig);
it->setPort("\\Y", module->addWire(NEW_ID, GetSize(old_sig))); it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig)));
} }
} else { } else {
module->addNotGate(NEW_ID, sig, old_sig); module->addNotGate(NEW_ID, sig, old_sig);
@ -537,7 +537,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
sig = module->addWire(NEW_ID); sig = module->addWire(NEW_ID);
} else } else
log_abort(); log_abort();
new_cell->setPort("\\" + port.first, sig); new_cell->setPort("\\" + port.first.str(), sig);
} }
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
@ -599,26 +599,26 @@ struct DfflibmapPass : public Pass {
LibertyParser libparser(f); LibertyParser libparser(f);
f.close(); f.close();
find_cell(libparser.ast, "$_DFF_N_", false, false, false, false, prepare_mode); find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, prepare_mode);
find_cell(libparser.ast, "$_DFF_P_", true, false, false, false, prepare_mode); find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, prepare_mode);
find_cell(libparser.ast, "$_DFF_NN0_", false, true, false, false, prepare_mode); find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, prepare_mode);
find_cell(libparser.ast, "$_DFF_NN1_", false, true, false, true, prepare_mode); find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, prepare_mode);
find_cell(libparser.ast, "$_DFF_NP0_", false, true, true, false, prepare_mode); find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, prepare_mode);
find_cell(libparser.ast, "$_DFF_NP1_", false, true, true, true, prepare_mode); find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, prepare_mode);
find_cell(libparser.ast, "$_DFF_PN0_", true, true, false, false, prepare_mode); find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, prepare_mode);
find_cell(libparser.ast, "$_DFF_PN1_", true, true, false, true, prepare_mode); find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, prepare_mode);
find_cell(libparser.ast, "$_DFF_PP0_", true, true, true, false, prepare_mode); find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, prepare_mode);
find_cell(libparser.ast, "$_DFF_PP1_", true, true, true, true, prepare_mode); find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_NNN_", false, false, false, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_NNP_", false, false, true, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_NPN_", false, true, false, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_NPP_", false, true, true, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_PNN_", true, false, false, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_PNP_", true, false, true, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_PPN_", true, true, false, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, prepare_mode);
find_cell_sr(libparser.ast, "$_DFFSR_PPP_", true, true, true, prepare_mode); find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, prepare_mode);
// try to implement as many cells as possible just by inverting // try to implement as many cells as possible just by inverting
// the SET and RESET pins. If necessary, implement cell types // the SET and RESET pins. If necessary, implement cell types
@ -642,23 +642,23 @@ struct DfflibmapPass : public Pass {
break; break;
} }
map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN0_"); map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN0_));
map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN1_"); map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN1_));
map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP0_"); map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP0_));
map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP1_"); map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP1_));
map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN0_"); map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN0_));
map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN1_"); map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN1_));
map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP0_"); map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP0_));
map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP1_"); map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP1_));
map_adff_to_dff("$_DFF_NN0_", "$_DFF_N_"); map_adff_to_dff(ID($_DFF_NN0_), ID($_DFF_N_));
map_adff_to_dff("$_DFF_NN1_", "$_DFF_N_"); map_adff_to_dff(ID($_DFF_NN1_), ID($_DFF_N_));
map_adff_to_dff("$_DFF_NP0_", "$_DFF_N_"); map_adff_to_dff(ID($_DFF_NP0_), ID($_DFF_N_));
map_adff_to_dff("$_DFF_NP1_", "$_DFF_N_"); map_adff_to_dff(ID($_DFF_NP1_), ID($_DFF_N_));
map_adff_to_dff("$_DFF_PN0_", "$_DFF_P_"); map_adff_to_dff(ID($_DFF_PN0_), ID($_DFF_P_));
map_adff_to_dff("$_DFF_PN1_", "$_DFF_P_"); map_adff_to_dff(ID($_DFF_PN1_), ID($_DFF_P_));
map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_"); map_adff_to_dff(ID($_DFF_PP0_), ID($_DFF_P_));
map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_"); map_adff_to_dff(ID($_DFF_PP1_), ID($_DFF_P_));
log(" final dff cell mappings:\n"); log(" final dff cell mappings:\n");
logmap_all(); logmap_all();

68
passes/techmap/dffsr2dff.cc
View File

@ -25,17 +25,17 @@ PRIVATE_NAMESPACE_BEGIN
void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell) void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
{ {
if (cell->type == "$dffsr") if (cell->type == ID($dffsr))
{ {
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID(WIDTH)).as_int();
bool setpol = cell->getParam("\\SET_POLARITY").as_bool(); bool setpol = cell->getParam(ID(SET_POLARITY)).as_bool();
bool clrpol = cell->getParam("\\CLR_POLARITY").as_bool(); bool clrpol = cell->getParam(ID(CLR_POLARITY)).as_bool();
SigBit setunused = setpol ? State::S0 : State::S1; SigBit setunused = setpol ? State::S0 : State::S1;
SigBit clrunused = clrpol ? State::S0 : State::S1; SigBit clrunused = clrpol ? State::S0 : State::S1;
SigSpec setsig = sigmap(cell->getPort("\\SET")); SigSpec setsig = sigmap(cell->getPort(ID(SET)));
SigSpec clrsig = sigmap(cell->getPort("\\CLR")); SigSpec clrsig = sigmap(cell->getPort(ID(CLR)));
Const reset_val; Const reset_val;
SigSpec setctrl, clrctrl; SigSpec setctrl, clrctrl;
@ -78,32 +78,32 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
if (GetSize(setctrl) == 1) { if (GetSize(setctrl) == 1) {
cell->setPort("\\ARST", setctrl); cell->setPort(ID(ARST), setctrl);
cell->setParam("\\ARST_POLARITY", setpol); cell->setParam(ID(ARST_POLARITY), setpol);
} else { } else {
cell->setPort("\\ARST", clrctrl); cell->setPort(ID(ARST), clrctrl);
cell->setParam("\\ARST_POLARITY", clrpol); cell->setParam(ID(ARST_POLARITY), clrpol);
} }
cell->type = "$adff"; cell->type = ID($adff);
cell->unsetPort("\\SET"); cell->unsetPort(ID(SET));
cell->unsetPort("\\CLR"); cell->unsetPort(ID(CLR));
cell->setParam("\\ARST_VALUE", reset_val); cell->setParam(ID(ARST_VALUE), reset_val);
cell->unsetParam("\\SET_POLARITY"); cell->unsetParam(ID(SET_POLARITY));
cell->unsetParam("\\CLR_POLARITY"); cell->unsetParam(ID(CLR_POLARITY));
return; return;
} }
if (cell->type.in("$_DFFSR_NNN_", "$_DFFSR_NNP_", "$_DFFSR_NPN_", "$_DFFSR_NPP_", if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
"$_DFFSR_PNN_", "$_DFFSR_PNP_", "$_DFFSR_PPN_", "$_DFFSR_PPP_")) ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
{ {
char clkpol = cell->type.c_str()[8]; char clkpol = cell->type.c_str()[8];
char setpol = cell->type.c_str()[9]; char setpol = cell->type.c_str()[9];
char clrpol = cell->type.c_str()[10]; char clrpol = cell->type.c_str()[10];
SigBit setbit = sigmap(cell->getPort("\\S")); SigBit setbit = sigmap(cell->getPort(ID(S)));
SigBit clrbit = sigmap(cell->getPort("\\R")); SigBit clrbit = sigmap(cell->getPort(ID(R)));
SigBit setunused = setpol == 'P' ? State::S0 : State::S1; SigBit setunused = setpol == 'P' ? State::S0 : State::S1;
SigBit clrunused = clrpol == 'P' ? State::S0 : State::S1; SigBit clrunused = clrpol == 'P' ? State::S0 : State::S1;
@ -112,14 +112,14 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
if (setbit == setunused) { if (setbit == setunused) {
cell->type = stringf("$_DFF_%c%c0_", clkpol, clrpol); cell->type = stringf("$_DFF_%c%c0_", clkpol, clrpol);
cell->unsetPort("\\S"); cell->unsetPort(ID(S));
goto converted_gate; goto converted_gate;
} }
if (clrbit == clrunused) { if (clrbit == clrunused) {
cell->type = stringf("$_DFF_%c%c1_", clkpol, setpol); cell->type = stringf("$_DFF_%c%c1_", clkpol, setpol);
cell->setPort("\\R", cell->getPort("\\S")); cell->setPort(ID(R), cell->getPort(ID(S)));
cell->unsetPort("\\S"); cell->unsetPort(ID(S));
goto converted_gate; goto converted_gate;
} }
@ -133,32 +133,32 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
void adff_worker(SigMap &sigmap, Module *module, Cell *cell) void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
{ {
if (cell->type == "$adff") if (cell->type == ID($adff))
{ {
bool rstpol = cell->getParam("\\ARST_POLARITY").as_bool(); bool rstpol = cell->getParam(ID(ARST_POLARITY)).as_bool();
SigBit rstunused = rstpol ? State::S0 : State::S1; SigBit rstunused = rstpol ? State::S0 : State::S1;
SigSpec rstsig = sigmap(cell->getPort("\\ARST")); SigSpec rstsig = sigmap(cell->getPort(ID(ARST)));
if (rstsig != rstunused) if (rstsig != rstunused)
return; return;
log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell)); log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell));
cell->type = "$dff"; cell->type = ID($dff);
cell->unsetPort("\\ARST"); cell->unsetPort(ID(ARST));
cell->unsetParam("\\ARST_VALUE"); cell->unsetParam(ID(ARST_VALUE));
cell->unsetParam("\\ARST_POLARITY"); cell->unsetParam(ID(ARST_POLARITY));
return; return;
} }
if (cell->type.in("$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_", if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
"$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_")) ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
{ {
char clkpol = cell->type.c_str()[6]; char clkpol = cell->type.c_str()[6];
char rstpol = cell->type.c_str()[7]; char rstpol = cell->type.c_str()[7];
SigBit rstbit = sigmap(cell->getPort("\\R")); SigBit rstbit = sigmap(cell->getPort(ID(R)));
SigBit rstunused = rstpol == 'P' ? State::S0 : State::S1; SigBit rstunused = rstpol == 'P' ? State::S0 : State::S1;
if (rstbit != rstunused) if (rstbit != rstunused)
@ -168,7 +168,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
log("Converting %s cell %s.%s to %s.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(newtype)); log("Converting %s cell %s.%s to %s.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(newtype));
cell->type = newtype; cell->type = newtype;
cell->unsetPort("\\R"); cell->unsetPort(ID(R));
return; return;
} }

62
passes/techmap/extract.cc
View File

@ -58,36 +58,36 @@ public:
return value; return value;
#define param_bool(_n) if (param == _n) return value.as_bool(); #define param_bool(_n) if (param == _n) return value.as_bool();
param_bool("\\ARST_POLARITY"); param_bool(ID(ARST_POLARITY));
param_bool("\\A_SIGNED"); param_bool(ID(A_SIGNED));
param_bool("\\B_SIGNED"); param_bool(ID(B_SIGNED));
param_bool("\\CLK_ENABLE"); param_bool(ID(CLK_ENABLE));
param_bool("\\CLK_POLARITY"); param_bool(ID(CLK_POLARITY));
param_bool("\\CLR_POLARITY"); param_bool(ID(CLR_POLARITY));
param_bool("\\EN_POLARITY"); param_bool(ID(EN_POLARITY));
param_bool("\\SET_POLARITY"); param_bool(ID(SET_POLARITY));
param_bool("\\TRANSPARENT"); param_bool(ID(TRANSPARENT));
#undef param_bool #undef param_bool
#define param_int(_n) if (param == _n) return value.as_int(); #define param_int(_n) if (param == _n) return value.as_int();
param_int("\\ABITS") param_int(ID(ABITS))
param_int("\\A_WIDTH") param_int(ID(A_WIDTH))
param_int("\\B_WIDTH") param_int(ID(B_WIDTH))
param_int("\\CTRL_IN_WIDTH") param_int(ID(CTRL_IN_WIDTH))
param_int("\\CTRL_OUT_WIDTH") param_int(ID(CTRL_OUT_WIDTH))
param_int("\\OFFSET") param_int(ID(OFFSET))
param_int("\\PRIORITY") param_int(ID(PRIORITY))
param_int("\\RD_PORTS") param_int(ID(RD_PORTS))
param_int("\\SIZE") param_int(ID(SIZE))
param_int("\\STATE_BITS") param_int(ID(STATE_BITS))
param_int("\\STATE_NUM") param_int(ID(STATE_NUM))
param_int("\\STATE_NUM_LOG2") param_int(ID(STATE_NUM_LOG2))
param_int("\\STATE_RST") param_int(ID(STATE_RST))
param_int("\\S_WIDTH") param_int(ID(S_WIDTH))
param_int("\\TRANS_NUM") param_int(ID(TRANS_NUM))
param_int("\\WIDTH") param_int(ID(WIDTH))
param_int("\\WR_PORTS") param_int(ID(WR_PORTS))
param_int("\\Y_WIDTH") param_int(ID(Y_WIDTH))
#undef param_int #undef param_int
return value; return value;
@ -341,10 +341,10 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit:
bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right) bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
{ {
int left_idx = 0, right_idx = 0; int left_idx = 0, right_idx = 0;
if (left->attributes.count("\\extract_order") > 0) if (left->attributes.count(ID(extract_order)) > 0)
left_idx = left->attributes.at("\\extract_order").as_int(); left_idx = left->attributes.at(ID(extract_order)).as_int();
if (right->attributes.count("\\extract_order") > 0) if (right->attributes.count(ID(extract_order)) > 0)
right_idx = right->attributes.at("\\extract_order").as_int(); right_idx = right->attributes.at(ID(extract_order)).as_int();
if (left_idx != right_idx) if (left_idx != right_idx)
return left_idx < right_idx; return left_idx < right_idx;
return left->name < right->name; return left->name < right->name;

152
passes/techmap/extract_counter.cc
View File

@ -120,71 +120,71 @@ int counter_tryextract(
//A counter with less than 2 bits makes no sense //A counter with less than 2 bits makes no sense
//TODO: configurable min threshold //TODO: configurable min threshold
int a_width = cell->getParam("\\A_WIDTH").as_int(); int a_width = cell->getParam(ID(A_WIDTH)).as_int();
extract.width = a_width; extract.width = a_width;
if( (a_width < 2) || (a_width > maxwidth) ) if( (a_width < 2) || (a_width > maxwidth) )
return 1; return 1;
//Second input must be a single bit //Second input must be a single bit
int b_width = cell->getParam("\\B_WIDTH").as_int(); int b_width = cell->getParam(ID(B_WIDTH)).as_int();
if(b_width != 1) if(b_width != 1)
return 2; return 2;
//Both inputs must be unsigned, so don't extract anything with a signed input //Both inputs must be unsigned, so don't extract anything with a signed input
bool a_sign = cell->getParam("\\A_SIGNED").as_bool(); bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool();
bool b_sign = cell->getParam("\\B_SIGNED").as_bool(); bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool();
if(a_sign || b_sign) if(a_sign || b_sign)
return 3; return 3;
//To be a counter, one input of the ALU must be a constant 1 //To be a counter, one input of the ALU must be a constant 1
//TODO: can A or B be swapped in synthesized RTL or is B always the 1? //TODO: can A or B be swapped in synthesized RTL or is B always the 1?
const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B")); const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID(B)));
if(!b_port.is_fully_const() || (b_port.as_int() != 1) ) if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
return 4; return 4;
//BI and CI must be constant 1 as well //BI and CI must be constant 1 as well
const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI")); const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) ) if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
return 5; return 5;
const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI")); const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) ) if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
return 6; return 6;
//CO and X must be unconnected (exactly one connection to each port) //CO and X must be unconnected (exactly one connection to each port)
if(!is_unconnected(sigmap(cell->getPort("\\CO")), index)) if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index))
return 7; return 7;
if(!is_unconnected(sigmap(cell->getPort("\\X")), index)) if(!is_unconnected(sigmap(cell->getPort(ID(X))), index))
return 8; return 8;
//Y must have exactly one connection, and it has to be a $mux cell. //Y must have exactly one connection, and it has to be a $mux cell.
//We must have a direct bus connection from our Y to their A. //We must have a direct bus connection from our Y to their A.
const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y")); const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID(Y)));
pool<Cell*> y_loads = get_other_cells(aluy, index, cell); pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
if(y_loads.size() != 1) if(y_loads.size() != 1)
return 9; return 9;
Cell* count_mux = *y_loads.begin(); Cell* count_mux = *y_loads.begin();
extract.count_mux = count_mux; extract.count_mux = count_mux;
if(count_mux->type != "$mux") if(count_mux->type != ID($mux))
return 10; return 10;
if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A")) if(!is_full_bus(aluy, index, cell, ID(Y), count_mux, ID(A)))
return 11; return 11;
//B connection of the mux is our underflow value //B connection of the mux is our underflow value
const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B")); const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID(B)));
if(!underflow.is_fully_const()) if(!underflow.is_fully_const())
return 12; return 12;
extract.count_value = underflow.as_int(); extract.count_value = underflow.as_int();
//S connection of the mux must come from an inverter (need not be the only load) //S connection of the mux must come from an inverter (need not be the only load)
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S")); const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S)));
extract.outsig = muxsel; extract.outsig = muxsel;
pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux); pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
Cell* underflow_inv = NULL; Cell* underflow_inv = NULL;
for(auto c : muxsel_conns) for(auto c : muxsel_conns)
{ {
if(c->type != "$logic_not") if(c->type != ID($logic_not))
continue; continue;
if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true)) if(!is_full_bus(muxsel, index, c, ID(Y), count_mux, ID(S), true))
continue; continue;
underflow_inv = c; underflow_inv = c;
@ -196,7 +196,7 @@ int counter_tryextract(
//Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable //Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable
//If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register //If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register
const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y")); const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(ID(Y)));
pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux); pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
if(muxy_loads.size() != 1) if(muxy_loads.size() != 1)
return 14; return 14;
@ -204,12 +204,12 @@ int counter_tryextract(
Cell* count_reg = muxload; Cell* count_reg = muxload;
Cell* cemux = NULL; Cell* cemux = NULL;
RTLIL::SigSpec cey; RTLIL::SigSpec cey;
if(muxload->type == "$mux") if(muxload->type == ID($mux))
{ {
//This mux is probably a clock enable mux. //This mux is probably a clock enable mux.
//Find our count register (should be our only load) //Find our count register (should be our only load)
cemux = muxload; cemux = muxload;
cey = sigmap(cemux->getPort("\\Y")); cey = sigmap(cemux->getPort(ID(Y)));
pool<Cell*> cey_loads = get_other_cells(cey, index, cemux); pool<Cell*> cey_loads = get_other_cells(cey, index, cemux);
if(cey_loads.size() != 1) if(cey_loads.size() != 1)
return 24; return 24;
@ -217,32 +217,32 @@ int counter_tryextract(
//Mux should have A driven by count Q, and B by muxy //Mux should have A driven by count Q, and B by muxy
//TODO: if A and B are swapped, CE polarity is inverted //TODO: if A and B are swapped, CE polarity is inverted
if(sigmap(cemux->getPort("\\B")) != muxy) if(sigmap(cemux->getPort(ID(B))) != muxy)
return 24; return 24;
if(sigmap(cemux->getPort("\\A")) != sigmap(count_reg->getPort("\\Q"))) if(sigmap(cemux->getPort(ID(A))) != sigmap(count_reg->getPort(ID(Q))))
return 24; return 24;
if(sigmap(cemux->getPort("\\Y")) != sigmap(count_reg->getPort("\\D"))) if(sigmap(cemux->getPort(ID(Y))) != sigmap(count_reg->getPort(ID(D))))
return 24; return 24;
//Select of the mux is our clock enable //Select of the mux is our clock enable
extract.has_ce = true; extract.has_ce = true;
extract.ce = sigmap(cemux->getPort("\\S")); extract.ce = sigmap(cemux->getPort(ID(S)));
} }
else else
extract.has_ce = false; extract.has_ce = false;
extract.count_reg = count_reg; extract.count_reg = count_reg;
if(count_reg->type == "$dff") if(count_reg->type == ID($dff))
extract.has_reset = false; extract.has_reset = false;
else if(count_reg->type == "$adff") else if(count_reg->type == ID($adff))
{ {
extract.has_reset = true; extract.has_reset = true;
//Check polarity of reset - we may have to add an inverter later on! //Check polarity of reset - we may have to add an inverter later on!
extract.rst_inverted = (count_reg->getParam("\\ARST_POLARITY").as_int() != 1); extract.rst_inverted = (count_reg->getParam(ID(ARST_POLARITY)).as_int() != 1);
//Verify ARST_VALUE is zero or full scale //Verify ARST_VALUE is zero or full scale
int rst_value = count_reg->getParam("\\ARST_VALUE").as_int(); int rst_value = count_reg->getParam(ID(ARST_VALUE)).as_int();
if(rst_value == 0) if(rst_value == 0)
extract.rst_to_max = false; extract.rst_to_max = false;
else if(rst_value == extract.count_value) else if(rst_value == extract.count_value)
@ -251,7 +251,7 @@ int counter_tryextract(
return 23; return 23;
//Save the reset //Save the reset
extract.rst = sigmap(count_reg->getPort("\\ARST")); extract.rst = sigmap(count_reg->getPort(ID(ARST)));
} }
//TODO: support synchronous reset //TODO: support synchronous reset
else else
@ -260,12 +260,12 @@ int counter_tryextract(
//Sanity check that we use the ALU output properly //Sanity check that we use the ALU output properly
if(extract.has_ce) if(extract.has_ce)
{ {
if(!is_full_bus(muxy, index, count_mux, "\\Y", cemux, "\\B")) if(!is_full_bus(muxy, index, count_mux, ID(Y), cemux, ID(B)))
return 16; return 16;
if(!is_full_bus(cey, index, cemux, "\\Y", count_reg, "\\D")) if(!is_full_bus(cey, index, cemux, ID(Y), count_reg, ID(D)))
return 16; return 16;
} }
else if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D")) else if(!is_full_bus(muxy, index, count_mux, ID(Y), count_reg, ID(D)))
return 16; return 16;
//TODO: Verify count_reg CLK_POLARITY is 1 //TODO: Verify count_reg CLK_POLARITY is 1
@ -273,7 +273,7 @@ int counter_tryextract(
//Register output must have exactly two loads, the inverter and ALU //Register output must have exactly two loads, the inverter and ALU
//(unless we have a parallel output!) //(unless we have a parallel output!)
//If we have a clock enable, 3 is OK //If we have a clock enable, 3 is OK
const RTLIL::SigSpec qport = count_reg->getPort("\\Q"); const RTLIL::SigSpec qport = count_reg->getPort(ID(Q));
const RTLIL::SigSpec cnout = sigmap(qport); const RTLIL::SigSpec cnout = sigmap(qport);
pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg); pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
unsigned int max_loads = 2; unsigned int max_loads = 2;
@ -312,19 +312,19 @@ int counter_tryextract(
} }
} }
} }
if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true)) if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID(A), true))
return 18; return 18;
if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true)) if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID(A), true))
return 19; return 19;
//Look up the clock from the register //Look up the clock from the register
extract.clk = sigmap(count_reg->getPort("\\CLK")); extract.clk = sigmap(count_reg->getPort(ID(CLK)));
//Register output net must have an INIT attribute equal to the count value //Register output net must have an INIT attribute equal to the count value
extract.rwire = cnout.as_wire(); extract.rwire = cnout.as_wire();
if(extract.rwire->attributes.find("\\init") == extract.rwire->attributes.end()) if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
return 20; return 20;
int rinit = extract.rwire->attributes["\\init"].as_int(); int rinit = extract.rwire->attributes[ID(init)].as_int();
if(rinit != extract.count_value) if(rinit != extract.count_value)
return 21; return 21;
@ -343,21 +343,21 @@ void counter_worker(
SigMap& sigmap = index.sigmap; SigMap& sigmap = index.sigmap;
//Core of the counter must be an ALU //Core of the counter must be an ALU
if (cell->type != "$alu") if (cell->type != ID($alu))
return; return;
//A input is the count value. Check if it has COUNT_EXTRACT set. //A input is the count value. Check if it has COUNT_EXTRACT set.
//If it's not a wire, don't even try //If it's not a wire, don't even try
auto port = sigmap(cell->getPort("\\A")); auto port = sigmap(cell->getPort(ID(A)));
if(!port.is_wire()) if(!port.is_wire())
return; return;
RTLIL::Wire* a_wire = port.as_wire(); RTLIL::Wire* a_wire = port.as_wire();
bool force_extract = false; bool force_extract = false;
bool never_extract = false; bool never_extract = false;
string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str(); string count_reg_src = a_wire->attributes[ID(src)].decode_string().c_str();
if(a_wire->attributes.find("\\COUNT_EXTRACT") != a_wire->attributes.end()) if(a_wire->attributes.find(ID(COUNT_EXTRACT)) != a_wire->attributes.end())
{ {
pool<string> sa = a_wire->get_strpool_attribute("\\COUNT_EXTRACT"); pool<string> sa = a_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
string extract_value; string extract_value;
if(sa.size() >= 1) if(sa.size() >= 1)
{ {
@ -434,66 +434,66 @@ void counter_worker(
string countname = string("$COUNTx$") + log_id(extract.rwire->name.str()); string countname = string("$COUNTx$") + log_id(extract.rwire->name.str());
//Wipe all of the old connections to the ALU //Wipe all of the old connections to the ALU
cell->unsetPort("\\A"); cell->unsetPort(ID(A));
cell->unsetPort("\\B"); cell->unsetPort(ID(B));
cell->unsetPort("\\BI"); cell->unsetPort(ID(BI));
cell->unsetPort("\\CI"); cell->unsetPort(ID(CI));
cell->unsetPort("\\CO"); cell->unsetPort(ID(CO));
cell->unsetPort("\\X"); cell->unsetPort(ID(X));
cell->unsetPort("\\Y"); cell->unsetPort(ID(Y));
cell->unsetParam("\\A_SIGNED"); cell->unsetParam(ID(A_SIGNED));
cell->unsetParam("\\A_WIDTH"); cell->unsetParam(ID(A_WIDTH));
cell->unsetParam("\\B_SIGNED"); cell->unsetParam(ID(B_SIGNED));
cell->unsetParam("\\B_WIDTH"); cell->unsetParam(ID(B_WIDTH));
cell->unsetParam("\\Y_WIDTH"); cell->unsetParam(ID(Y_WIDTH));
//Change the cell type //Change the cell type
cell->type = "$__COUNT_"; cell->type = ID($__COUNT_);
//Hook up resets //Hook up resets
if(extract.has_reset) if(extract.has_reset)
{ {
//TODO: support other kinds of reset //TODO: support other kinds of reset
cell->setParam("\\RESET_MODE", RTLIL::Const("LEVEL")); cell->setParam(ID(RESET_MODE), RTLIL::Const("LEVEL"));
//If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset) //If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset)
if(extract.rst_inverted) if(extract.rst_inverted)
{ {
auto realreset = cell->module->addWire(NEW_ID); auto realreset = cell->module->addWire(NEW_ID);
cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset)); cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset));
cell->setPort("\\RST", realreset); cell->setPort(ID(RST), realreset);
} }
else else
cell->setPort("\\RST", extract.rst); cell->setPort(ID(RST), extract.rst);
} }
else else
{ {
cell->setParam("\\RESET_MODE", RTLIL::Const("RISING")); cell->setParam(ID(RESET_MODE), RTLIL::Const("RISING"));
cell->setPort("\\RST", RTLIL::SigSpec(false)); cell->setPort(ID(RST), RTLIL::SigSpec(false));
} }
//Hook up other stuff //Hook up other stuff
//cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); //cell->setParam(ID(CLKIN_DIVIDE), RTLIL::Const(1));
cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value)); cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value));
cell->setParam("\\WIDTH", RTLIL::Const(extract.width)); cell->setParam(ID(WIDTH), RTLIL::Const(extract.width));
cell->setPort("\\CLK", extract.clk); cell->setPort(ID(CLK), extract.clk);
cell->setPort("\\OUT", extract.outsig); cell->setPort(ID(OUT), extract.outsig);
//Hook up clock enable //Hook up clock enable
if(extract.has_ce) if(extract.has_ce)
{ {
cell->setParam("\\HAS_CE", RTLIL::Const(1)); cell->setParam(ID(HAS_CE), RTLIL::Const(1));
cell->setPort("\\CE", extract.ce); cell->setPort(ID(CE), extract.ce);
} }
else else
cell->setParam("\\HAS_CE", RTLIL::Const(0)); cell->setParam(ID(HAS_CE), RTLIL::Const(0));
//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output //Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
cell->setParam("\\HAS_POUT", RTLIL::Const(0)); cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
cell->setParam("\\RESET_TO_MAX", RTLIL::Const(0)); cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
cell->setParam("\\DIRECTION", RTLIL::Const("DOWN")); cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
cell->setPort("\\CE", RTLIL::Const(1)); cell->setPort(ID(CE), RTLIL::Const(1));
cell->setPort("\\UP", RTLIL::Const(0)); cell->setPort(ID(UP), RTLIL::Const(0));
//Hook up any parallel outputs //Hook up any parallel outputs
for(auto load : extract.pouts) for(auto load : extract.pouts)
@ -505,8 +505,8 @@ void counter_worker(
//Connect it to our parallel output //Connect it to our parallel output
//(this is OK to do more than once b/c they all go to the same place) //(this is OK to do more than once b/c they all go to the same place)
cell->setPort("\\POUT", sig); cell->setPort(ID(POUT), sig);
cell->setParam("\\HAS_POUT", RTLIL::Const(1)); cell->setParam(ID(HAS_POUT), RTLIL::Const(1));
} }
//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires) //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
@ -546,7 +546,7 @@ void counter_worker(
int newbits = ceil(log2(extract.count_value)); int newbits = ceil(log2(extract.count_value));
if(extract.width != newbits) if(extract.width != newbits)
{ {
cell->setParam("\\WIDTH", RTLIL::Const(newbits)); cell->setParam(ID(WIDTH), RTLIL::Const(newbits));
log(" Optimizing out %d unused high-order bits (new width is %d)\n", log(" Optimizing out %d unused high-order bits (new width is %d)\n",
extract.width - newbits, extract.width - newbits,
newbits); newbits);

50
passes/techmap/extract_fa.cc
View File

@ -85,11 +85,11 @@ struct ExtractFaWorker
{ {
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", if (cell->type.in( ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", "$_NMUX_", ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
"$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{ {
SigBit y = sigmap(SigBit(cell->getPort("\\Y"))); SigBit y = sigmap(SigBit(cell->getPort(ID(Y))));
log_assert(driver.count(y) == 0); log_assert(driver.count(y) == 0);
driver[y] = cell; driver[y] = cell;
} }
@ -262,10 +262,10 @@ struct ExtractFaWorker
pool<SigBit> new_leaves = leaves; pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit); new_leaves.erase(bit);
if (cell->hasPort("\\A")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\A")))); if (cell->hasPort(ID(A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(A)))));
if (cell->hasPort("\\B")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\B")))); if (cell->hasPort(ID(B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(B)))));
if (cell->hasPort("\\C")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\C")))); if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C)))));
if (cell->hasPort("\\D")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\D")))); if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D)))));
if (GetSize(new_leaves) > maxbreadth) if (GetSize(new_leaves) > maxbreadth)
continue; continue;
@ -277,8 +277,8 @@ struct ExtractFaWorker
void assign_new_driver(SigBit bit, SigBit new_driver) void assign_new_driver(SigBit bit, SigBit new_driver)
{ {
Cell *cell = driver.at(bit); Cell *cell = driver.at(bit);
if (sigmap(cell->getPort("\\Y")) == bit) { if (sigmap(cell->getPort(ID(Y))) == bit) {
cell->setPort("\\Y", module->addWire(NEW_ID)); cell->setPort(ID(Y), module->addWire(NEW_ID));
module->connect(bit, new_driver); module->connect(bit, new_driver);
} }
} }
@ -289,7 +289,7 @@ struct ExtractFaWorker
for (auto it : driver) for (auto it : driver)
{ {
if (it.second->type.in("$_BUF_", "$_NOT_")) if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
continue; continue;
SigBit root = it.first; SigBit root = it.first;
@ -390,20 +390,20 @@ struct ExtractFaWorker
} }
else else
{ {
Cell *cell = module->addCell(NEW_ID, "$fa"); Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", 1); cell->setParam(ID(WIDTH), 1);
log(" Created $fa cell %s.\n", log_id(cell)); log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort("\\A", f3i.inv_a ? module->NotGate(NEW_ID, A) : A); cell->setPort(ID(A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort("\\B", f3i.inv_b ? module->NotGate(NEW_ID, B) : B); cell->setPort(ID(B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort("\\C", f3i.inv_c ? module->NotGate(NEW_ID, C) : C); cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID); X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID); Y = module->addWire(NEW_ID);
cell->setPort("\\X", X); cell->setPort(ID(X), X);
cell->setPort("\\Y", Y); cell->setPort(ID(Y), Y);
facache[fakey] = make_tuple(X, Y, cell); facache[fakey] = make_tuple(X, Y, cell);
} }
@ -496,20 +496,20 @@ struct ExtractFaWorker
} }
else else
{ {
Cell *cell = module->addCell(NEW_ID, "$fa"); Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", 1); cell->setParam(ID(WIDTH), 1);
log(" Created $fa cell %s.\n", log_id(cell)); log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort("\\A", f2i.inv_a ? module->NotGate(NEW_ID, A) : A); cell->setPort(ID(A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort("\\B", f2i.inv_b ? module->NotGate(NEW_ID, B) : B); cell->setPort(ID(B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort("\\C", State::S0); cell->setPort(ID(C), State::S0);
X = module->addWire(NEW_ID); X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID); Y = module->addWire(NEW_ID);
cell->setPort("\\X", X); cell->setPort(ID(X), X);
cell->setPort("\\Y", Y); cell->setPort(ID(Y), Y);
} }
if (func2.at(key).count(xor2_func)) { if (func2.at(key).count(xor2_func)) {

44
passes/techmap/extract_reduce.cc
View File

@ -58,9 +58,9 @@ struct ExtractReducePass : public Pass
inline bool IsRightType(Cell* cell, GateType gt) inline bool IsRightType(Cell* cell, GateType gt)
{ {
return (cell->type == "$_AND_" && gt == GateType::And) || return (cell->type == ID($_AND_) && gt == GateType::And) ||
(cell->type == "$_OR_" && gt == GateType::Or) || (cell->type == ID($_OR_) && gt == GateType::Or) ||
(cell->type == "$_XOR_" && gt == GateType::Xor); (cell->type == ID($_XOR_) && gt == GateType::Xor);
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -124,11 +124,11 @@ struct ExtractReducePass : public Pass
GateType gt; GateType gt;
if (cell->type == "$_AND_") if (cell->type == ID($_AND_))
gt = GateType::And; gt = GateType::And;
else if (cell->type == "$_OR_") else if (cell->type == ID($_OR_))
gt = GateType::Or; gt = GateType::Or;
else if (cell->type == "$_XOR_") else if (cell->type == ID($_XOR_))
gt = GateType::Xor; gt = GateType::Xor;
else else
continue; continue;
@ -148,7 +148,7 @@ struct ExtractReducePass : public Pass
head_cell = x; head_cell = x;
auto y = sigmap(x->getPort("\\Y")); auto y = sigmap(x->getPort(ID(Y)));
log_assert(y.size() == 1); log_assert(y.size() == 1);
// Should only continue if there is one fanout back into a cell (not to a port) // Should only continue if there is one fanout back into a cell (not to a port)
@ -166,7 +166,7 @@ struct ExtractReducePass : public Pass
{ {
//BFS, following all chains until they hit a cell of a different type //BFS, following all chains until they hit a cell of a different type
//Pick the longest one //Pick the longest one
auto y = sigmap(cell->getPort("\\Y")); auto y = sigmap(cell->getPort(ID(Y)));
pool<Cell*> current_loads = sig_to_sink[y]; pool<Cell*> current_loads = sig_to_sink[y];
pool<Cell*> next_loads; pool<Cell*> next_loads;
@ -233,7 +233,7 @@ struct ExtractReducePass : public Pass
cur_supercell.insert(x); cur_supercell.insert(x);
auto a = sigmap(x->getPort("\\A")); auto a = sigmap(x->getPort(ID(A)));
log_assert(a.size() == 1); log_assert(a.size() == 1);
// Must have only one sink unless we're going off chain // Must have only one sink unless we're going off chain
@ -249,7 +249,7 @@ struct ExtractReducePass : public Pass
} }
} }
auto b = sigmap(x->getPort("\\B")); auto b = sigmap(x->getPort(ID(B)));
log_assert(b.size() == 1); log_assert(b.size() == 1);
// Must have only one sink // Must have only one sink
@ -279,26 +279,26 @@ struct ExtractReducePass : public Pass
pool<SigBit> input_pool_intermed; pool<SigBit> input_pool_intermed;
for (auto x : cur_supercell) for (auto x : cur_supercell)
{ {
input_pool.insert(sigmap(x->getPort("\\A"))[0]); input_pool.insert(sigmap(x->getPort(ID(A)))[0]);
input_pool.insert(sigmap(x->getPort("\\B"))[0]); input_pool.insert(sigmap(x->getPort(ID(B)))[0]);
input_pool_intermed.insert(sigmap(x->getPort("\\Y"))[0]); input_pool_intermed.insert(sigmap(x->getPort(ID(Y)))[0]);
} }
SigSpec input; SigSpec input;
for (auto b : input_pool) for (auto b : input_pool)
if (input_pool_intermed.count(b) == 0) if (input_pool_intermed.count(b) == 0)
input.append_bit(b); input.append_bit(b);
SigBit output = sigmap(head_cell->getPort("\\Y")[0]); SigBit output = sigmap(head_cell->getPort(ID(Y))[0]);
auto new_reduce_cell = module->addCell(NEW_ID, auto new_reduce_cell = module->addCell(NEW_ID,
gt == GateType::And ? "$reduce_and" : gt == GateType::And ? ID($reduce_and) :
gt == GateType::Or ? "$reduce_or" : gt == GateType::Or ? ID($reduce_or) :
gt == GateType::Xor ? "$reduce_xor" : ""); gt == GateType::Xor ? ID($reduce_xor) : "");
new_reduce_cell->setParam("\\A_SIGNED", 0); new_reduce_cell->setParam(ID(A_SIGNED), 0);
new_reduce_cell->setParam("\\A_WIDTH", input.size()); new_reduce_cell->setParam(ID(A_WIDTH), input.size());
new_reduce_cell->setParam("\\Y_WIDTH", 1); new_reduce_cell->setParam(ID(Y_WIDTH), 1);
new_reduce_cell->setPort("\\A", input); new_reduce_cell->setPort(ID(A), input);
new_reduce_cell->setPort("\\Y", output); new_reduce_cell->setPort(ID(Y), output);
if(allow_off_chain) if(allow_off_chain)
consumed_cells.insert(head_cell); consumed_cells.insert(head_cell);

8
passes/techmap/flowmap.cc
View File

@ -671,8 +671,8 @@ struct FlowmapWorker
labels[node] = -1; labels[node] = -1;
for (auto input : inputs) for (auto input : inputs)
{ {
if (input.wire->attributes.count("\\$flowmap_level")) if (input.wire->attributes.count(ID($flowmap_level)))
labels[input] = input.wire->attributes["\\$flowmap_level"].as_int(); labels[input] = input.wire->attributes[ID($flowmap_level)].as_int();
else else
labels[input] = 0; labels[input] = 0;
} }
@ -1412,7 +1412,7 @@ struct FlowmapWorker
for (auto gate_node : lut_gates[node]) for (auto gate_node : lut_gates[node])
{ {
auto gate_origin = node_origins[gate_node]; auto gate_origin = node_origins[gate_node];
lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src")); lut->add_strpool_attribute(ID(src), gate_origin.cell->get_strpool_attribute(ID(src)));
packed_count++; packed_count++;
} }
lut_count++; lut_count++;
@ -1586,7 +1586,7 @@ struct FlowmapPass : public Pass {
} }
else else
{ {
cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"}; cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)};
} }
const char *algo_r = relax ? "-r" : ""; const char *algo_r = relax ? "-r" : "";

16
passes/techmap/iopadmap.cc
View File

@ -179,8 +179,8 @@ struct IopadmapPass : public Pass {
SigMap rewrites; SigMap rewrites;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == "$_TBUF_") { if (cell->type == ID($_TBUF_)) {
SigBit bit = sigmap(cell->getPort("\\Y").as_bit()); SigBit bit = sigmap(cell->getPort(ID(Y)).as_bit());
tbuf_bits[bit].first = cell->name; tbuf_bits[bit].first = cell->name;
} }
@ -212,8 +212,8 @@ struct IopadmapPass : public Pass {
if (tbuf_cell == nullptr) if (tbuf_cell == nullptr)
continue; continue;
SigBit en_sig = tbuf_cell->getPort("\\E").as_bit(); SigBit en_sig = tbuf_cell->getPort(ID(E)).as_bit();
SigBit data_sig = tbuf_cell->getPort("\\A").as_bit(); SigBit data_sig = tbuf_cell->getPort(ID(A)).as_bit();
if (wire->port_input && !tinoutpad_celltype.empty()) if (wire->port_input && !tinoutpad_celltype.empty())
{ {
@ -226,7 +226,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire); cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig); cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit); cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
cell->attributes["\\keep"] = RTLIL::Const(1); cell->attributes[ID(keep)] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) { for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn); auto c = module->cell(cn);
@ -263,7 +263,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig); cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit); cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
cell->attributes["\\keep"] = RTLIL::Const(1); cell->attributes[ID(keep)] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) { for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn); auto c = module->cell(cn);
@ -390,7 +390,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
cell->attributes["\\keep"] = RTLIL::Const(1); cell->attributes[ID(keep)] = RTLIL::Const(1);
} }
} }
else else
@ -403,7 +403,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes["\\keep"] = RTLIL::Const(1); cell->attributes[ID(keep)] = RTLIL::Const(1);
} }
wire->port_id = 0; wire->port_id = 0;

8
passes/techmap/lut2mux.cc
View File

@ -25,9 +25,9 @@ PRIVATE_NAMESPACE_BEGIN
int lut2mux(Cell *cell) int lut2mux(Cell *cell)
{ {
SigSpec sig_a = cell->getPort("\\A"); SigSpec sig_a = cell->getPort(ID(A));
SigSpec sig_y = cell->getPort("\\Y"); SigSpec sig_y = cell->getPort(ID(Y));
Const lut = cell->getParam("\\LUT"); Const lut = cell->getParam(ID(LUT));
int count = 1; int count = 1;
if (GetSize(sig_a) == 1) if (GetSize(sig_a) == 1)
@ -81,7 +81,7 @@ struct Lut2muxPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
if (cell->type == "$lut") { if (cell->type == ID($lut)) {
IdString cell_name = cell->name; IdString cell_name = cell->name;
int count = lut2mux(cell); int count = lut2mux(cell);
log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count); log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);

50
passes/techmap/maccmap.cc
View File

@ -111,13 +111,13 @@ struct MaccmapWorker
RTLIL::Wire *w1 = module->addWire(NEW_ID, width); RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width); RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", width); cell->setParam(ID(WIDTH), width);
cell->setPort("\\A", in1); cell->setPort(ID(A), in1);
cell->setPort("\\B", in2); cell->setPort(ID(B), in2);
cell->setPort("\\C", in3); cell->setPort(ID(C), in3);
cell->setPort("\\Y", w1); cell->setPort(ID(Y), w1);
cell->setPort("\\X", w2); cell->setPort(ID(X), w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb}; out1 = {out_zeros_msb, w1, out_zeros_lsb};
out2 = {out_zeros_msb, w2, out_zeros_lsb}; out2 = {out_zeros_msb, w2, out_zeros_lsb};
@ -237,23 +237,23 @@ struct MaccmapWorker
} }
RTLIL::Cell *c = module->addCell(NEW_ID, "$alu"); RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
c->setPort("\\A", summands.front()); c->setPort(ID(A), summands.front());
c->setPort("\\B", summands.back()); c->setPort(ID(B), summands.back());
c->setPort("\\CI", State::S0); c->setPort(ID(CI), State::S0);
c->setPort("\\BI", State::S0); c->setPort(ID(BI), State::S0);
c->setPort("\\Y", module->addWire(NEW_ID, width)); c->setPort(ID(Y), module->addWire(NEW_ID, width));
c->setPort("\\X", module->addWire(NEW_ID, width)); c->setPort(ID(X), module->addWire(NEW_ID, width));
c->setPort("\\CO", module->addWire(NEW_ID, width)); c->setPort(ID(CO), module->addWire(NEW_ID, width));
c->fixup_parameters(); c->fixup_parameters();
if (!tree_sum_bits.empty()) { if (!tree_sum_bits.empty()) {
c->setPort("\\CI", tree_sum_bits.back()); c->setPort(ID(CI), tree_sum_bits.back());
tree_sum_bits.pop_back(); tree_sum_bits.pop_back();
} }
log_assert(tree_sum_bits.empty()); log_assert(tree_sum_bits.empty());
return c->getPort("\\Y"); return c->getPort(ID(Y));
} }
}; };
@ -264,17 +264,17 @@ extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false
void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
{ {
int width = GetSize(cell->getPort("\\Y")); int width = GetSize(cell->getPort(ID(Y)));
Macc macc; Macc macc;
macc.from_cell(cell); macc.from_cell(cell);
RTLIL::SigSpec all_input_bits; RTLIL::SigSpec all_input_bits;
all_input_bits.append(cell->getPort("\\A")); all_input_bits.append(cell->getPort(ID(A)));
all_input_bits.append(cell->getPort("\\B")); all_input_bits.append(cell->getPort(ID(B)));
if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) { if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) {
module->connect(cell->getPort("\\Y"), RTLIL::SigSpec(RTLIL::Sx, width)); module->connect(cell->getPort(ID(Y)), RTLIL::SigSpec(RTLIL::Sx, width));
return; return;
} }
@ -339,9 +339,9 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
} }
if (summands.front().second) if (summands.front().second)
module->addNeg(NEW_ID, summands.front().first, cell->getPort("\\Y")); module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID(Y)));
else else
module->connect(cell->getPort("\\Y"), summands.front().first); module->connect(cell->getPort(ID(Y)), summands.front().first);
} }
else else
{ {
@ -356,7 +356,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &bit : macc.bit_ports) for (auto &bit : macc.bit_ports)
worker.add(bit, 0); worker.add(bit, 0);
module->connect(cell->getPort("\\Y"), worker.synth()); module->connect(cell->getPort(ID(Y)), worker.synth());
} }
} }
@ -393,7 +393,7 @@ struct MaccmapPass : public Pass {
for (auto mod : design->selected_modules()) for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells()) for (auto cell : mod->selected_cells())
if (cell->type == "$macc") { if (cell->type == ID($macc)) {
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type)); log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
maccmap(mod, cell, unmap_mode); maccmap(mod, cell, unmap_mode);
mod->remove(cell); mod->remove(cell);

106
passes/techmap/muxcover.cc
View File

@ -116,13 +116,13 @@ struct MuxcoverWorker
if (!cell->input(conn.first)) if (!cell->input(conn.first))
continue; continue;
for (auto bit : sigmap(conn.second)) { for (auto bit : sigmap(conn.second)) {
if (used_once.count(bit) || cell->type != "$_MUX_" || conn.first == "\\S") if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID(S))
roots.insert(bit); roots.insert(bit);
used_once.insert(bit); used_once.insert(bit);
} }
} }
if (cell->type == "$_MUX_") if (cell->type == ID($_MUX_))
sig_to_mux[sigmap(cell->getPort("\\Y"))] = cell; sig_to_mux[sigmap(cell->getPort(ID(Y)))] = cell;
} }
log(" Treeifying %d MUXes:\n", GetSize(sig_to_mux)); log(" Treeifying %d MUXes:\n", GetSize(sig_to_mux));
@ -141,8 +141,8 @@ struct MuxcoverWorker
if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) { if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) {
Cell *c = sig_to_mux.at(bit); Cell *c = sig_to_mux.at(bit);
tree.muxes[bit] = c; tree.muxes[bit] = c;
wavefront.insert(sigmap(c->getPort("\\A"))); wavefront.insert(sigmap(c->getPort(ID(A))));
wavefront.insert(sigmap(c->getPort("\\B"))); wavefront.insert(sigmap(c->getPort(ID(B))));
} }
} }
@ -516,69 +516,69 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) { if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++; count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_ID, "$_MUX_"); Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
cell->setPort("\\A", mux.inputs[0]); cell->setPort(ID(A), mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]); cell->setPort(ID(B), mux.inputs[1]);
cell->setPort("\\S", mux.selects[0]); cell->setPort(ID(S), mux.selects[0]);
cell->setPort("\\Y", bit); cell->setPort(ID(Y), bit);
return; return;
} }
if (GetSize(mux.inputs) == 4) { if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++; count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_ID, "$_MUX4_"); Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
cell->setPort("\\A", mux.inputs[0]); cell->setPort(ID(A), mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]); cell->setPort(ID(B), mux.inputs[1]);
cell->setPort("\\C", mux.inputs[2]); cell->setPort(ID(C), mux.inputs[2]);
cell->setPort("\\D", mux.inputs[3]); cell->setPort(ID(D), mux.inputs[3]);
cell->setPort("\\S", mux.selects[0]); cell->setPort(ID(S), mux.selects[0]);
cell->setPort("\\T", mux.selects[1]); cell->setPort(ID(T), mux.selects[1]);
cell->setPort("\\Y", bit); cell->setPort(ID(Y), bit);
return; return;
} }
if (GetSize(mux.inputs) == 8) { if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++; count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_ID, "$_MUX8_"); Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
cell->setPort("\\A", mux.inputs[0]); cell->setPort(ID(A), mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]); cell->setPort(ID(B), mux.inputs[1]);
cell->setPort("\\C", mux.inputs[2]); cell->setPort(ID(C), mux.inputs[2]);
cell->setPort("\\D", mux.inputs[3]); cell->setPort(ID(D), mux.inputs[3]);
cell->setPort("\\E", mux.inputs[4]); cell->setPort(ID(E), mux.inputs[4]);
cell->setPort("\\F", mux.inputs[5]); cell->setPort(ID(F), mux.inputs[5]);
cell->setPort("\\G", mux.inputs[6]); cell->setPort(ID(G), mux.inputs[6]);
cell->setPort("\\H", mux.inputs[7]); cell->setPort(ID(H), mux.inputs[7]);
cell->setPort("\\S", mux.selects[0]); cell->setPort(ID(S), mux.selects[0]);
cell->setPort("\\T", mux.selects[1]); cell->setPort(ID(T), mux.selects[1]);
cell->setPort("\\U", mux.selects[2]); cell->setPort(ID(U), mux.selects[2]);
cell->setPort("\\Y", bit); cell->setPort(ID(Y), bit);
return; return;
} }
if (GetSize(mux.inputs) == 16) { if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++; count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_ID, "$_MUX16_"); Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
cell->setPort("\\A", mux.inputs[0]); cell->setPort(ID(A), mux.inputs[0]);
cell->setPort("\\B", mux.inputs[1]); cell->setPort(ID(B), mux.inputs[1]);
cell->setPort("\\C", mux.inputs[2]); cell->setPort(ID(C), mux.inputs[2]);
cell->setPort("\\D", mux.inputs[3]); cell->setPort(ID(D), mux.inputs[3]);
cell->setPort("\\E", mux.inputs[4]); cell->setPort(ID(E), mux.inputs[4]);
cell->setPort("\\F", mux.inputs[5]); cell->setPort(ID(F), mux.inputs[5]);
cell->setPort("\\G", mux.inputs[6]); cell->setPort(ID(G), mux.inputs[6]);
cell->setPort("\\H", mux.inputs[7]); cell->setPort(ID(H), mux.inputs[7]);
cell->setPort("\\I", mux.inputs[8]); cell->setPort(ID(I), mux.inputs[8]);
cell->setPort("\\J", mux.inputs[9]); cell->setPort(ID(J), mux.inputs[9]);
cell->setPort("\\K", mux.inputs[10]); cell->setPort(ID(K), mux.inputs[10]);
cell->setPort("\\L", mux.inputs[11]); cell->setPort(ID(L), mux.inputs[11]);
cell->setPort("\\M", mux.inputs[12]); cell->setPort(ID(M), mux.inputs[12]);
cell->setPort("\\N", mux.inputs[13]); cell->setPort(ID(N), mux.inputs[13]);
cell->setPort("\\O", mux.inputs[14]); cell->setPort(ID(O), mux.inputs[14]);
cell->setPort("\\P", mux.inputs[15]); cell->setPort(ID(P), mux.inputs[15]);
cell->setPort("\\S", mux.selects[0]); cell->setPort(ID(S), mux.selects[0]);
cell->setPort("\\T", mux.selects[1]); cell->setPort(ID(T), mux.selects[1]);
cell->setPort("\\U", mux.selects[2]); cell->setPort(ID(U), mux.selects[2]);
cell->setPort("\\V", mux.selects[3]); cell->setPort(ID(V), mux.selects[3]);
cell->setPort("\\Y", bit); cell->setPort(ID(Y), bit);
return; return;
} }

6
passes/techmap/nlutmap.cc
View File

@ -82,10 +82,10 @@ struct NlutmapWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type != "$lut" || mapped_cells.count(cell)) if (cell->type != ID($lut) || mapped_cells.count(cell))
continue; continue;
if (GetSize(cell->getPort("\\A")) == lut_size || lut_size == 2) if (GetSize(cell->getPort(ID(A))) == lut_size || lut_size == 2)
candidate_ratings[cell] = 0; candidate_ratings[cell] = 0;
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
@ -119,7 +119,7 @@ struct NlutmapWorker
if (config.assert_mode) { if (config.assert_mode) {
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == "$lut" && !mapped_cells.count(cell)) if (cell->type == ID($lut) && !mapped_cells.count(cell))
log_error("Insufficient number of LUTs to map all logic cells!\n"); log_error("Insufficient number of LUTs to map all logic cells!\n");
} }

12
passes/techmap/pmuxtree.cc
View File

@ -89,21 +89,21 @@ struct PmuxtreePass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type != "$pmux") if (cell->type != ID($pmux))
continue; continue;
SigSpec sig_data = cell->getPort("\\B"); SigSpec sig_data = cell->getPort(ID(B));
SigSpec sig_sel = cell->getPort("\\S"); SigSpec sig_sel = cell->getPort(ID(S));
if (!cell->getPort("\\A").is_fully_undef()) { if (!cell->getPort(ID(A)).is_fully_undef()) {
sig_data.append(cell->getPort("\\A")); sig_data.append(cell->getPort(ID(A)));
SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel); SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
sig_sel.append(module->Not(NEW_ID, sig_sel_or)); sig_sel.append(module->Not(NEW_ID, sig_sel_or));
} }
SigSpec result, result_or; SigSpec result, result_or;
result = recursive_mux_generator(module, sig_data, sig_sel, result_or); result = recursive_mux_generator(module, sig_data, sig_sel, result_or);
module->connect(cell->getPort("\\Y"), result); module->connect(cell->getPort(ID(Y)), result);
module->remove(cell); module->remove(cell);
} }
} }

134
passes/techmap/shregmap.cc
View File

@ -73,22 +73,22 @@ struct ShregmapTechGreenpak4 : ShregmapTech
bool fixup(Cell *cell, dict<int, SigBit> &taps) bool fixup(Cell *cell, dict<int, SigBit> &taps)
{ {
auto D = cell->getPort("\\D"); auto D = cell->getPort(ID(D));
auto C = cell->getPort("\\C"); auto C = cell->getPort(ID(C));
auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG"); auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
newcell->setPort("\\nRST", State::S1); newcell->setPort(ID(nRST), State::S1);
newcell->setPort("\\CLK", C); newcell->setPort(ID(CLK), C);
newcell->setPort("\\IN", D); newcell->setPort(ID(IN), D);
int i = 0; int i = 0;
for (auto tap : taps) { for (auto tap : taps) {
newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second); newcell->setPort(i ? ID(OUTB) : ID(OUTA), tap.second);
newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1); newcell->setParam(i ? ID(OUTB_TAP) : ID(OUTA_TAP), tap.first + 1);
i++; i++;
} }
cell->setParam("\\OUTA_INVERT", 0); cell->setParam(ID(OUTA_INVERT), 0);
return false; return false;
} }
}; };
@ -104,19 +104,19 @@ struct ShregmapTechXilinx7 : ShregmapTech
{ {
for (const auto &i : module->cells_) { for (const auto &i : module->cells_) {
auto cell = i.second; auto cell = i.second;
if (cell->type == "$shiftx") { if (cell->type == ID($shiftx)) {
if (cell->getParam("\\Y_WIDTH") != 1) continue; if (cell->getParam(ID(Y_WIDTH)) != 1) continue;
int j = 0; int j = 0;
for (auto bit : sigmap(cell->getPort("\\A"))) for (auto bit : sigmap(cell->getPort(ID(A))))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0); sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
log_assert(j == cell->getParam("\\A_WIDTH").as_int()); log_assert(j == cell->getParam(ID(A_WIDTH)).as_int());
} }
else if (cell->type == "$mux") { else if (cell->type == ID($mux)) {
int j = 0; int j = 0;
for (auto bit : sigmap(cell->getPort("\\A"))) for (auto bit : sigmap(cell->getPort(ID(A))))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++); sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
j = 0; j = 0;
for (auto bit : sigmap(cell->getPort("\\B"))) for (auto bit : sigmap(cell->getPort(ID(B))))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++); sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
} }
} }
@ -128,9 +128,9 @@ struct ShregmapTechXilinx7 : ShregmapTech
if (it == sigbit_to_shiftx_offset.end()) if (it == sigbit_to_shiftx_offset.end())
return; return;
if (cell) { if (cell) {
if (cell->type == "$shiftx" && port == "\\A") if (cell->type == ID($shiftx) && port == ID(A))
return; return;
if (cell->type == "$mux" && (port == "\\A" || port == "\\B")) if (cell->type == ID($mux) && port.in(ID(A), ID(B)))
return; return;
} }
sigbit_to_shiftx_offset.erase(it); sigbit_to_shiftx_offset.erase(it);
@ -177,21 +177,21 @@ struct ShregmapTechXilinx7 : ShregmapTech
log_assert(shiftx); log_assert(shiftx);
// Only map if $shiftx exclusively covers the shift register // Only map if $shiftx exclusively covers the shift register
if (shiftx->type == "$shiftx") { if (shiftx->type == ID($shiftx)) {
if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int()) if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int())
return false; return false;
// Due to padding the most significant bits of A may be 1'bx, // Due to padding the most significant bits of A may be 1'bx,
// and if so, discount them // and if so, discount them
if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) { if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) {
const SigSpec A = shiftx->getPort("\\A"); const SigSpec A = shiftx->getPort(ID(A));
const int A_width = shiftx->getParam("\\A_WIDTH").as_int(); const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int();
for (int i = GetSize(taps); i < A_width; ++i) for (int i = GetSize(taps); i < A_width; ++i)
if (A[i] != RTLIL::Sx) return false; if (A[i] != RTLIL::Sx) return false;
} }
else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int())
return false; return false;
} }
else if (shiftx->type == "$mux") { else if (shiftx->type == ID($mux)) {
if (GetSize(taps) != 2) if (GetSize(taps) != 2)
return false; return false;
} }
@ -208,34 +208,34 @@ struct ShregmapTechXilinx7 : ShregmapTech
auto it = sigbit_to_shiftx_offset.find(bit); auto it = sigbit_to_shiftx_offset.find(bit);
log_assert(it != sigbit_to_shiftx_offset.end()); log_assert(it != sigbit_to_shiftx_offset.end());
auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_"); auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_));
newcell->set_src_attribute(cell->get_src_attribute()); newcell->set_src_attribute(cell->get_src_attribute());
newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH)));
newcell->setParam("\\INIT", cell->getParam("\\INIT")); newcell->setParam(ID(INIT), cell->getParam(ID(INIT)));
newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL")); newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL)));
newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL")); newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL)));
newcell->setPort("\\C", cell->getPort("\\C")); newcell->setPort(ID(C), cell->getPort(ID(C)));
newcell->setPort("\\D", cell->getPort("\\D")); newcell->setPort(ID(D), cell->getPort(ID(D)));
if (cell->hasPort("\\E")) if (cell->hasPort(ID(E)))
newcell->setPort("\\E", cell->getPort("\\E")); newcell->setPort(ID(E), cell->getPort(ID(E)));
Cell* shiftx = std::get<0>(it->second); Cell* shiftx = std::get<0>(it->second);
RTLIL::SigSpec l_wire, q_wire; RTLIL::SigSpec l_wire, q_wire;
if (shiftx->type == "$shiftx") { if (shiftx->type == ID($shiftx)) {
l_wire = shiftx->getPort("\\B"); l_wire = shiftx->getPort(ID(B));
q_wire = shiftx->getPort("\\Y"); q_wire = shiftx->getPort(ID(Y));
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
} }
else if (shiftx->type == "$mux") { else if (shiftx->type == ID($mux)) {
l_wire = shiftx->getPort("\\S"); l_wire = shiftx->getPort(ID(S));
q_wire = shiftx->getPort("\\Y"); q_wire = shiftx->getPort(ID(Y));
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
} }
else log_abort(); else log_abort();
newcell->setPort("\\Q", q_wire); newcell->setPort(ID(Q), q_wire);
newcell->setPort("\\L", l_wire); newcell->setPort(ID(L), l_wire);
return false; return false;
} }
@ -263,16 +263,16 @@ struct ShregmapWorker
{ {
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->port_output || wire->get_bool_attribute("\\keep")) { if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
for (auto bit : sigmap(wire)) { for (auto bit : sigmap(wire)) {
sigbit_with_non_chain_users.insert(bit); sigbit_with_non_chain_users.insert(bit);
if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
} }
} }
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID(init))) {
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 && !opts.zinit) if (initval[i] == State::S0 && !opts.zinit)
sigbit_init[initsig[i]] = false; sigbit_init[initsig[i]] = false;
@ -283,7 +283,7 @@ struct ShregmapWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep")) if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep)))
{ {
IdString d_port = opts.ffcells.at(cell->type).first; IdString d_port = opts.ffcells.at(cell->type).first;
IdString q_port = opts.ffcells.at(cell->type).second; IdString q_port = opts.ffcells.at(cell->type).second;
@ -474,7 +474,7 @@ struct ShregmapWorker
initval.push_back(State::S0); initval.push_back(State::S0);
remove_init.insert(bit); remove_init.insert(bit);
} }
first_cell->setParam("\\INIT", initval); first_cell->setParam(ID(INIT), initval);
} }
if (opts.zinit) if (opts.zinit)
@ -488,22 +488,22 @@ struct ShregmapWorker
int param_clkpol = -1; int param_clkpol = -1;
int param_enpol = 2; int param_enpol = 2;
if (first_cell->type == "$_DFF_N_") param_clkpol = 0; if (first_cell->type == ID($_DFF_N_)) param_clkpol = 0;
if (first_cell->type == "$_DFF_P_") param_clkpol = 1; if (first_cell->type == ID($_DFF_P_)) param_clkpol = 1;
if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0; if (first_cell->type == ID($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1; if (first_cell->type == ID($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0; if (first_cell->type == ID($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1; if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
log_assert(param_clkpol >= 0); log_assert(param_clkpol >= 0);
first_cell->setParam("\\CLKPOL", param_clkpol); first_cell->setParam(ID(CLKPOL), param_clkpol);
if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol); if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
} }
first_cell->type = shreg_cell_type_str; first_cell->type = shreg_cell_type_str;
first_cell->setPort(q_port, last_cell->getPort(q_port)); first_cell->setPort(q_port, last_cell->getPort(q_port));
first_cell->setParam("\\DEPTH", depth); first_cell->setParam(ID(DEPTH), depth);
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
remove_cells.insert(first_cell); remove_cells.insert(first_cell);
@ -521,18 +521,18 @@ struct ShregmapWorker
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count("\\init") == 0) if (wire->attributes.count(ID(init)) == 0)
continue; continue;
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
Const &initval = wire->attributes.at("\\init"); Const &initval = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
if (remove_init.count(initsig[i])) if (remove_init.count(initsig[i]))
initval[i] = State::Sx; initval[i] = State::Sx;
if (SigSpec(initval).is_fully_undef()) if (SigSpec(initval).is_fully_undef())
wire->attributes.erase("\\init"); wire->attributes.erase(ID(init));
} }
remove_cells.clear(); remove_cells.clear();
@ -717,19 +717,19 @@ struct ShregmapPass : public Pass {
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none"; bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none) if (clk_pos && en_none)
opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
if (clk_neg && en_none) if (clk_neg && en_none)
opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
if (clk_pos && en_pos) if (clk_pos && en_pos)
opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
if (clk_pos && en_neg) if (clk_pos && en_neg)
opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
if (clk_neg && en_pos) if (clk_neg && en_pos)
opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
if (clk_neg && en_neg) if (clk_neg && en_neg)
opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
if (en_pos || en_neg) if (en_pos || en_neg)
opts.ffe = true; opts.ffe = true;

462
passes/techmap/simplemap.cc
View File

@ -28,82 +28,82 @@ YOSYS_NAMESPACE_BEGIN
void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a[i]); gate->setPort(ID(A), sig_a[i]);
gate->setPort("\\Y", sig_y[i]); gate->setPort(ID(Y), sig_y[i]);
} }
} }
void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a)); module->connect(RTLIL::SigSig(sig_y, sig_a));
} }
void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID(B_SIGNED)).as_bool());
if (cell->type == "$xnor") if (cell->type == ID($xnor))
{ {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y)); RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_t[i]); gate->setPort(ID(A), sig_t[i]);
gate->setPort("\\Y", sig_y[i]); gate->setPort(ID(Y), sig_y[i]);
} }
sig_y = sig_t; sig_y = sig_t;
} }
std::string gate_type; IdString gate_type;
if (cell->type == "$and") gate_type = "$_AND_"; if (cell->type == ID($and)) gate_type = ID($_AND_);
if (cell->type == "$or") gate_type = "$_OR_"; if (cell->type == ID($or)) gate_type = ID($_OR_);
if (cell->type == "$xor") gate_type = "$_XOR_"; if (cell->type == ID($xor)) gate_type = ID($_XOR_);
if (cell->type == "$xnor") gate_type = "$_XOR_"; if (cell->type == ID($xnor)) gate_type = ID($_XOR_);
log_assert(!gate_type.empty()); log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a[i]); gate->setPort(ID(A), sig_a[i]);
gate->setPort("\\B", sig_b[i]); gate->setPort(ID(B), sig_b[i]);
gate->setPort("\\Y", sig_y[i]); gate->setPort(ID(Y), sig_y[i]);
} }
} }
void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
if (sig_y.size() == 0) if (sig_y.size() == 0)
return; return;
if (sig_a.size() == 0) { if (sig_a.size() == 0) {
if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == "$reduce_xor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
return; return;
} }
@ -112,12 +112,12 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1); sig_y = sig_y.extract(0, 1);
} }
std::string gate_type; IdString gate_type;
if (cell->type == "$reduce_and") gate_type = "$_AND_"; if (cell->type == ID($reduce_and)) gate_type = ID($_AND_);
if (cell->type == "$reduce_or") gate_type = "$_OR_"; if (cell->type == ID($reduce_or)) gate_type = ID($_OR_);
if (cell->type == "$reduce_xor") gate_type = "$_XOR_"; if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_);
if (cell->type == "$reduce_xnor") gate_type = "$_XOR_"; if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
if (cell->type == "$reduce_bool") gate_type = "$_OR_"; if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
log_assert(!gate_type.empty()); log_assert(!gate_type.empty());
RTLIL::Cell *last_output_cell = NULL; RTLIL::Cell *last_output_cell = NULL;
@ -134,22 +134,22 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
} }
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a[i]); gate->setPort(ID(A), sig_a[i]);
gate->setPort("\\B", sig_a[i+1]); gate->setPort(ID(B), sig_a[i+1]);
gate->setPort("\\Y", sig_t[i/2]); gate->setPort(ID(Y), sig_t[i/2]);
last_output_cell = gate; last_output_cell = gate;
} }
sig_a = sig_t; sig_a = sig_t;
} }
if (cell->type == "$reduce_xnor") { if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a); gate->setPort(ID(A), sig_a);
gate->setPort("\\Y", sig_t); gate->setPort(ID(Y), sig_t);
last_output_cell = gate; last_output_cell = gate;
sig_a = sig_t; sig_a = sig_t;
} }
@ -157,7 +157,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (last_output_cell == NULL) { if (last_output_cell == NULL) {
module->connect(RTLIL::SigSig(sig_y, sig_a)); module->connect(RTLIL::SigSig(sig_y, sig_a));
} else { } else {
last_output_cell->setPort("\\Y", sig_y); last_output_cell->setPort(ID(Y), sig_y);
} }
} }
@ -174,11 +174,11 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue; continue;
} }
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig[i]); gate->setPort(ID(A), sig[i]);
gate->setPort("\\B", sig[i+1]); gate->setPort(ID(B), sig[i+1]);
gate->setPort("\\Y", sig_t[i/2]); gate->setPort(ID(Y), sig_t[i/2]);
} }
sig = sig_t; sig = sig_t;
@ -190,10 +190,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
logic_reduce(module, sig_a, cell); logic_reduce(module, sig_a, cell);
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
if (sig_y.size() == 0) if (sig_y.size() == 0)
return; return;
@ -203,21 +203,21 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1); sig_y = sig_y.extract(0, 1);
} }
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a); gate->setPort(ID(A), sig_a);
gate->setPort("\\Y", sig_y); gate->setPort(ID(Y), sig_y);
} }
void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
logic_reduce(module, sig_a, cell); logic_reduce(module, sig_a, cell);
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
logic_reduce(module, sig_b, cell); logic_reduce(module, sig_b, cell);
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
if (sig_y.size() == 0) if (sig_y.size() == 0)
return; return;
@ -227,41 +227,41 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1); sig_y = sig_y.extract(0, 1);
} }
std::string gate_type; IdString gate_type;
if (cell->type == "$logic_and") gate_type = "$_AND_"; if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
if (cell->type == "$logic_or") gate_type = "$_OR_"; if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty()); log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a); gate->setPort(ID(A), sig_a);
gate->setPort("\\B", sig_b); gate->setPort(ID(B), sig_b);
gate->setPort("\\Y", sig_y); gate->setPort(ID(Y), sig_y);
} }
void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
bool is_ne = cell->type.in("$ne", "$nex"); bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); xor_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
simplemap_bitop(module, xor_cell); simplemap_bitop(module, xor_cell);
module->remove(xor_cell); module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
reduce_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); reduce_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
simplemap_reduce(module, reduce_cell); simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell); module->remove(reduce_cell);
if (!is_ne) { if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
not_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); not_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
simplemap_lognot(module, not_cell); simplemap_lognot(module, not_cell);
module->remove(not_cell); module->remove(not_cell);
} }
@ -269,65 +269,65 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort(ID(B));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a[i]); gate->setPort(ID(A), sig_a[i]);
gate->setPort("\\B", sig_b[i]); gate->setPort(ID(B), sig_b[i]);
gate->setPort("\\S", cell->getPort("\\S")); gate->setPort(ID(S), cell->getPort(ID(S)));
gate->setPort("\\Y", sig_y[i]); gate->setPort(ID(Y), sig_y[i]);
} }
} }
void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_e = cell->getPort("\\EN"); RTLIL::SigSpec sig_e = cell->getPort(ID(EN));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_TBUF_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", sig_a[i]); gate->setPort(ID(A), sig_a[i]);
gate->setPort("\\E", sig_e); gate->setPort(ID(E), sig_e);
gate->setPort("\\Y", sig_y[i]); gate->setPort(ID(Y), sig_y[i]);
} }
} }
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
SigSpec lut_ctrl = cell->getPort("\\A"); SigSpec lut_ctrl = cell->getPort(ID(A));
SigSpec lut_data = cell->getParam("\\LUT"); SigSpec lut_data = cell->getParam(ID(LUT));
lut_data.extend_u0(1 << cell->getParam("\\WIDTH").as_int()); lut_data.extend_u0(1 << cell->getParam(ID(WIDTH)).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) { for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec sig_s = lut_ctrl[idx]; SigSpec sig_s = lut_ctrl[idx];
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) { for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_"); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\A", lut_data[i]); gate->setPort(ID(A), lut_data[i]);
gate->setPort("\\B", lut_data[i+1]); gate->setPort(ID(B), lut_data[i+1]);
gate->setPort("\\S", lut_ctrl[idx]); gate->setPort(ID(S), lut_ctrl[idx]);
gate->setPort("\\Y", new_lut_data[i/2]); gate->setPort(ID(Y), new_lut_data[i/2]);
} }
lut_data = new_lut_data; lut_data = new_lut_data;
} }
module->connect(cell->getPort("\\Y"), lut_data); module->connect(cell->getPort(ID(Y)), lut_data);
} }
void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
SigSpec ctrl = cell->getPort("\\A"); SigSpec ctrl = cell->getPort(ID(A));
SigSpec table = cell->getParam("\\TABLE"); SigSpec table = cell->getParam(ID(TABLE));
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID(WIDTH)).as_int();
int depth = cell->getParam("\\DEPTH").as_int(); int depth = cell->getParam(ID(DEPTH)).as_int();
table.extend_u0(2 * width * depth); table.extend_u0(2 * width * depth);
SigSpec products; SigSpec products;
@ -348,213 +348,213 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1); products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
} }
module->connect(cell->getPort("\\Y"), module->ReduceOr(NEW_ID, products)); module->connect(cell->getPort(ID(Y)), module->ReduceOr(NEW_ID, products));
} }
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int offset = cell->parameters.at("\\OFFSET").as_int(); int offset = cell->parameters.at(ID(OFFSET)).as_int();
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort(ID(A));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
} }
void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
RTLIL::SigSpec sig_ab = cell->getPort("\\A"); RTLIL::SigSpec sig_ab = cell->getPort(ID(A));
sig_ab.append(cell->getPort("\\B")); sig_ab.append(cell->getPort(ID(B)));
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
module->connect(RTLIL::SigSig(sig_y, sig_ab)); module->connect(RTLIL::SigSig(sig_y, sig_ab));
} }
void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_s = cell->getPort("\\SET"); RTLIL::SigSpec sig_s = cell->getPort(ID(SET));
RTLIL::SigSpec sig_r = cell->getPort("\\CLR"); RTLIL::SigSpec sig_r = cell->getPort(ID(CLR));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\S", sig_s[i]); gate->setPort(ID(S), sig_s[i]);
gate->setPort("\\R", sig_r[i]); gate->setPort(ID(R), sig_r[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type = "$_FF_"; IdString gate_type = ID($_FF_);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\D", sig_d[i]); gate->setPort(ID(D), sig_d[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type = stringf("$_DFF_%c_", clk_pol); IdString gate_type = stringf("$_DFF_%c_", clk_pol);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\C", sig_clk); gate->setPort(ID(C), sig_clk);
gate->setPort("\\D", sig_d[i]); gate->setPort(ID(D), sig_d[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_en = cell->getPort("\\EN"); RTLIL::SigSpec sig_en = cell->getPort(ID(EN));
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol); IdString gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\C", sig_clk); gate->setPort(ID(C), sig_clk);
gate->setPort("\\E", sig_en); gate->setPort(ID(E), sig_en);
gate->setPort("\\D", sig_d[i]); gate->setPort(ID(D), sig_d[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_s = cell->getPort("\\SET"); RTLIL::SigSpec sig_s = cell->getPort(ID(SET));
RTLIL::SigSpec sig_r = cell->getPort("\\CLR"); RTLIL::SigSpec sig_r = cell->getPort(ID(CLR));
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); IdString gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\C", sig_clk); gate->setPort(ID(C), sig_clk);
gate->setPort("\\S", sig_s[i]); gate->setPort(ID(S), sig_s[i]);
gate->setPort("\\R", sig_r[i]); gate->setPort(ID(R), sig_r[i]);
gate->setPort("\\D", sig_d[i]); gate->setPort(ID(D), sig_d[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
char rst_pol = cell->parameters.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N'; char rst_pol = cell->parameters.at(ID(ARST_POLARITY)).as_bool() ? 'P' : 'N';
std::vector<RTLIL::State> rst_val = cell->parameters.at("\\ARST_VALUE").bits; std::vector<RTLIL::State> rst_val = cell->parameters.at(ID(ARST_VALUE)).bits;
while (int(rst_val.size()) < width) while (int(rst_val.size()) < width)
rst_val.push_back(RTLIL::State::S0); rst_val.push_back(RTLIL::State::S0);
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_rst = cell->getPort("\\ARST"); RTLIL::SigSpec sig_rst = cell->getPort(ID(ARST));
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0); RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\C", sig_clk); gate->setPort(ID(C), sig_clk);
gate->setPort("\\R", sig_rst); gate->setPort(ID(R), sig_rst);
gate->setPort("\\D", sig_d[i]); gate->setPort(ID(D), sig_d[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID(WIDTH)).as_int();
char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_en = cell->getPort("\\EN"); RTLIL::SigSpec sig_en = cell->getPort(ID(EN));
RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort("\\Q"); RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
std::string gate_type = stringf("$_DLATCH_%c_", en_pol); IdString gate_type = stringf("$_DLATCH_%c_", en_pol);
for (int i = 0; i < width; i++) { for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort("\\E", sig_en); gate->setPort(ID(E), sig_en);
gate->setPort("\\D", sig_d[i]); gate->setPort(ID(D), sig_d[i]);
gate->setPort("\\Q", sig_q[i]); gate->setPort(ID(Q), sig_q[i]);
} }
} }
void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers) void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{ {
mappers["$not"] = simplemap_not; mappers[ID($not)] = simplemap_not;
mappers["$pos"] = simplemap_pos; mappers[ID($pos)] = simplemap_pos;
mappers["$and"] = simplemap_bitop; mappers[ID($and)] = simplemap_bitop;
mappers["$or"] = simplemap_bitop; mappers[ID($or)] = simplemap_bitop;
mappers["$xor"] = simplemap_bitop; mappers[ID($xor)] = simplemap_bitop;
mappers["$xnor"] = simplemap_bitop; mappers[ID($xnor)] = simplemap_bitop;
mappers["$reduce_and"] = simplemap_reduce; mappers[ID($reduce_and)] = simplemap_reduce;
mappers["$reduce_or"] = simplemap_reduce; mappers[ID($reduce_or)] = simplemap_reduce;
mappers["$reduce_xor"] = simplemap_reduce; mappers[ID($reduce_xor)] = simplemap_reduce;
mappers["$reduce_xnor"] = simplemap_reduce; mappers[ID($reduce_xnor)] = simplemap_reduce;
mappers["$reduce_bool"] = simplemap_reduce; mappers[ID($reduce_bool)] = simplemap_reduce;
mappers["$logic_not"] = simplemap_lognot; mappers[ID($logic_not)] = simplemap_lognot;
mappers["$logic_and"] = simplemap_logbin; mappers[ID($logic_and)] = simplemap_logbin;
mappers["$logic_or"] = simplemap_logbin; mappers[ID($logic_or)] = simplemap_logbin;
mappers["$eq"] = simplemap_eqne; mappers[ID($eq)] = simplemap_eqne;
mappers["$eqx"] = simplemap_eqne; mappers[ID($eqx)] = simplemap_eqne;
mappers["$ne"] = simplemap_eqne; mappers[ID($ne)] = simplemap_eqne;
mappers["$nex"] = simplemap_eqne; mappers[ID($nex)] = simplemap_eqne;
mappers["$mux"] = simplemap_mux; mappers[ID($mux)] = simplemap_mux;
mappers["$tribuf"] = simplemap_tribuf; mappers[ID($tribuf)] = simplemap_tribuf;
mappers["$lut"] = simplemap_lut; mappers[ID($lut)] = simplemap_lut;
mappers["$sop"] = simplemap_sop; mappers[ID($sop)] = simplemap_sop;
mappers["$slice"] = simplemap_slice; mappers[ID($slice)] = simplemap_slice;
mappers["$concat"] = simplemap_concat; mappers[ID($concat)] = simplemap_concat;
mappers["$sr"] = simplemap_sr; mappers[ID($sr)] = simplemap_sr;
mappers["$ff"] = simplemap_ff; mappers[ID($ff)] = simplemap_ff;
mappers["$dff"] = simplemap_dff; mappers[ID($dff)] = simplemap_dff;
mappers["$dffe"] = simplemap_dffe; mappers[ID($dffe)] = simplemap_dffe;
mappers["$dffsr"] = simplemap_dffsr; mappers[ID($dffsr)] = simplemap_dffsr;
mappers["$adff"] = simplemap_adff; mappers[ID($adff)] = simplemap_adff;
mappers["$dlatch"] = simplemap_dlatch; mappers[ID($dlatch)] = simplemap_dlatch;
} }
void simplemap(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)

104
passes/techmap/techmap.cc
View File

@ -39,20 +39,20 @@ YOSYS_NAMESPACE_END
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
void apply_prefix(std::string prefix, std::string &id) void apply_prefix(IdString prefix, IdString &id)
{ {
if (id[0] == '\\') if (id[0] == '\\')
id = prefix + "." + id.substr(1); id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
else else
id = "$techmap" + prefix + "." + id; id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
} }
void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{ {
vector<SigChunk> chunks = sig; vector<SigChunk> chunks = sig;
for (auto &chunk : chunks) for (auto &chunk : chunks)
if (chunk.wire != NULL) { if (chunk.wire != NULL) {
std::string wire_name = chunk.wire->name.str(); IdString wire_name = chunk.wire->name;
apply_prefix(prefix, wire_name); apply_prefix(prefix, wire_name);
log_assert(module->wires_.count(wire_name) > 0); log_assert(module->wires_.count(wire_name) > 0);
chunk.wire = module->wires_[wire_name]; chunk.wire = module->wires_[wire_name];
@ -145,8 +145,8 @@ struct TechmapWorker
record.wire = it.second; record.wire = it.second;
record.value = it.second; record.value = it.second;
result[p].push_back(record); result[p].push_back(record);
it.second->attributes["\\keep"] = RTLIL::Const(1); it.second->attributes[ID(keep)] = RTLIL::Const(1);
it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1); it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
} }
} }
@ -175,11 +175,11 @@ struct TechmapWorker
} }
std::string orig_cell_name; std::string orig_cell_name;
pool<string> extra_src_attrs = cell->get_strpool_attribute("\\src"); pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
if (!flatten_mode) { if (!flatten_mode) {
for (auto &it : tpl->cells_) for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") { if (it.first == ID(_TECHMAP_REPLACE_)) {
orig_cell_name = cell->name.str(); orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break; break;
@ -189,16 +189,16 @@ struct TechmapWorker
dict<IdString, IdString> memory_renames; dict<IdString, IdString> memory_renames;
for (auto &it : tpl->memories) { for (auto &it : tpl->memories) {
std::string m_name = it.first.str(); IdString m_name = it.first;
apply_prefix(cell->name.str(), m_name); apply_prefix(cell->name, m_name);
RTLIL::Memory *m = new RTLIL::Memory; RTLIL::Memory *m = new RTLIL::Memory;
m->name = m_name; m->name = m_name;
m->width = it.second->width; m->width = it.second->width;
m->start_offset = it.second->start_offset; m->start_offset = it.second->start_offset;
m->size = it.second->size; m->size = it.second->size;
m->attributes = it.second->attributes; m->attributes = it.second->attributes;
if (m->attributes.count("\\src")) if (m->attributes.count(ID(src)))
m->add_strpool_attribute("\\src", extra_src_attrs); m->add_strpool_attribute(ID(src), extra_src_attrs);
module->memories[m->name] = m; module->memories[m->name] = m;
memory_renames[it.first] = m->name; memory_renames[it.first] = m->name;
design->select(module, m); design->select(module, m);
@ -209,16 +209,16 @@ struct TechmapWorker
for (auto &it : tpl->wires_) { for (auto &it : tpl->wires_) {
if (it.second->port_id > 0) if (it.second->port_id > 0)
positional_ports[stringf("$%d", it.second->port_id)] = it.first; positional_ports[stringf("$%d", it.second->port_id)] = it.first;
std::string w_name = it.second->name.str(); IdString w_name = it.second->name;
apply_prefix(cell->name.str(), w_name); apply_prefix(cell->name, w_name);
RTLIL::Wire *w = module->addWire(w_name, it.second); RTLIL::Wire *w = module->addWire(w_name, it.second);
w->port_input = false; w->port_input = false;
w->port_output = false; w->port_output = false;
w->port_id = 0; w->port_id = 0;
if (it.second->get_bool_attribute("\\_techmap_special_")) if (it.second->get_bool_attribute(ID(_techmap_special_)))
w->attributes.clear(); w->attributes.clear();
if (w->attributes.count("\\src")) if (w->attributes.count(ID(src)))
w->add_strpool_attribute("\\src", extra_src_attrs); w->add_strpool_attribute(ID(src), extra_src_attrs);
design->select(module, w); design->select(module, w);
} }
@ -257,18 +257,18 @@ struct TechmapWorker
if (w->port_output && !w->port_input) { if (w->port_output && !w->port_input) {
c.first = it.second; c.first = it.second;
c.second = RTLIL::SigSpec(w); c.second = RTLIL::SigSpec(w);
apply_prefix(cell->name.str(), c.second, module); apply_prefix(cell->name, c.second, module);
extra_connect.first = c.second; extra_connect.first = c.second;
extra_connect.second = c.first; extra_connect.second = c.first;
} else if (!w->port_output && w->port_input) { } else if (!w->port_output && w->port_input) {
c.first = RTLIL::SigSpec(w); c.first = RTLIL::SigSpec(w);
c.second = it.second; c.second = it.second;
apply_prefix(cell->name.str(), c.first, module); apply_prefix(cell->name, c.first, module);
extra_connect.first = c.first; extra_connect.first = c.first;
extra_connect.second = c.second; extra_connect.second = c.second;
} else { } else {
SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second; SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
apply_prefix(cell->name.str(), sig_tpl_pf, module); apply_prefix(cell->name, sig_tpl_pf, module);
for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) { if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
c.first.append(sig_mod[i]); c.first.append(sig_mod[i]);
@ -320,7 +320,7 @@ struct TechmapWorker
} }
for (auto &attr : w->attributes) { for (auto &attr : w->attributes) {
if (attr.first == "\\src") if (attr.first == ID(src))
continue; continue;
module->connect(extra_connect); module->connect(extra_connect);
break; break;
@ -330,13 +330,13 @@ struct TechmapWorker
for (auto &it : tpl->cells_) for (auto &it : tpl->cells_)
{ {
std::string c_name = it.second->name.str(); IdString c_name = it.second->name.str();
bool techmap_replace_cell = (!flatten_mode) && (c_name == "\\_TECHMAP_REPLACE_"); bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
if (techmap_replace_cell) if (techmap_replace_cell)
c_name = orig_cell_name; c_name = orig_cell_name;
else else
apply_prefix(cell->name.str(), c_name); apply_prefix(cell->name, c_name);
RTLIL::Cell *c = module->addCell(c_name, it.second); RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c); design->select(module, c);
@ -345,24 +345,24 @@ struct TechmapWorker
c->type = c->type.substr(1); c->type = c->type.substr(1);
for (auto &it2 : c->connections_) { for (auto &it2 : c->connections_) {
apply_prefix(cell->name.str(), it2.second, module); apply_prefix(cell->name, it2.second, module);
port_signal_map.apply(it2.second); port_signal_map.apply(it2.second);
} }
if (c->type == "$memrd" || c->type == "$memwr" || c->type == "$meminit") { if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
IdString memid = c->getParam("\\MEMID").decode_string(); IdString memid = c->getParam(ID(MEMID)).decode_string();
log_assert(memory_renames.count(memid) != 0); log_assert(memory_renames.count(memid) != 0);
c->setParam("\\MEMID", Const(memory_renames[memid].str())); c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
} }
if (c->type == "$mem") { if (c->type == ID($mem)) {
string memid = c->getParam("\\MEMID").decode_string(); IdString memid = c->getParam(ID(MEMID)).decode_string();
apply_prefix(cell->name.str(), memid); apply_prefix(cell->name, memid);
c->setParam("\\MEMID", Const(memid)); c->setParam(ID(MEMID), Const(memid.c_str()));
} }
if (c->attributes.count("\\src")) if (c->attributes.count(ID(src)))
c->add_strpool_attribute("\\src", extra_src_attrs); c->add_strpool_attribute(ID(src), extra_src_attrs);
if (techmap_replace_cell) if (techmap_replace_cell)
for (auto attr : cell->attributes) for (auto attr : cell->attributes)
@ -416,9 +416,9 @@ struct TechmapWorker
} }
if (flatten_mode) { if (flatten_mode) {
bool keepit = cell->get_bool_attribute("\\keep_hierarchy"); bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
for (auto &tpl_name : celltypeMap.at(cell_type)) for (auto &tpl_name : celltypeMap.at(cell_type))
if (map->modules_[tpl_name]->get_bool_attribute("\\keep_hierarchy")) if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
keepit = true; keepit = true;
if (keepit) { if (keepit) {
if (!flatten_keep_list[cell]) { if (!flatten_keep_list[cell]) {
@ -484,13 +484,13 @@ struct TechmapWorker
{ {
std::string extmapper_name; std::string extmapper_name;
if (tpl->get_bool_attribute("\\techmap_simplemap")) if (tpl->get_bool_attribute(ID(techmap_simplemap)))
extmapper_name = "simplemap"; extmapper_name = "simplemap";
if (tpl->get_bool_attribute("\\techmap_maccmap")) if (tpl->get_bool_attribute(ID(techmap_maccmap)))
extmapper_name = "maccmap"; extmapper_name = "maccmap";
if (tpl->attributes.count("\\techmap_wrap")) if (tpl->attributes.count(ID(techmap_wrap)))
extmapper_name = "wrap"; extmapper_name = "wrap";
if (!extmapper_name.empty()) if (!extmapper_name.empty())
@ -505,7 +505,7 @@ struct TechmapWorker
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
if (extmapper_name == "wrap") if (extmapper_name == "wrap")
m_name += ":" + sha1(tpl->attributes.at("\\techmap_wrap").decode_string()); m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
RTLIL::Module *extmapper_module = extmapper_design->module(m_name); RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
@ -520,7 +520,7 @@ struct TechmapWorker
int port_counter = 1; int port_counter = 1;
for (auto &c : extmapper_cell->connections_) { for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (w->name == "\\Y" || w->name == "\\Q") if (w->name.in(ID(Y), ID(Q)))
w->port_output = true; w->port_output = true;
else else
w->port_input = true; w->port_input = true;
@ -541,14 +541,14 @@ struct TechmapWorker
if (extmapper_name == "maccmap") { if (extmapper_name == "maccmap") {
log("Creating %s with maccmap.\n", log_id(extmapper_module)); log("Creating %s with maccmap.\n", log_id(extmapper_module));
if (extmapper_cell->type != "$macc") if (extmapper_cell->type != ID($macc))
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
maccmap(extmapper_module, extmapper_cell); maccmap(extmapper_module, extmapper_cell);
extmapper_module->remove(extmapper_cell); extmapper_module->remove(extmapper_cell);
} }
if (extmapper_name == "wrap") { if (extmapper_name == "wrap") {
std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string(); std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
mkdebug.on(); mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
@ -587,7 +587,7 @@ struct TechmapWorker
} }
if (extmapper_name == "maccmap") { if (extmapper_name == "maccmap") {
if (cell->type != "$macc") if (cell->type != ID($macc))
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
maccmap(module, cell); maccmap(module, cell);
} }
@ -616,8 +616,8 @@ struct TechmapWorker
continue; continue;
} }
if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
for (auto conn : cell->connections()) { for (auto conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
@ -656,8 +656,8 @@ struct TechmapWorker
bits = i; bits = i;
// Increment index by one to get number of bits // Increment index by one to get number of bits
bits++; bits++;
if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_")) if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits; parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
for (auto conn : cell->connections()) for (auto conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
@ -1136,8 +1136,8 @@ struct TechmapPass : public Pass {
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap; std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : map->modules_) { for (auto &it : map->modules_) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) { if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str()); char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n")) for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
celltypeMap[RTLIL::escape_id(q)].insert(it.first); celltypeMap[RTLIL::escape_id(q)].insert(it.first);
free(p); free(p);
@ -1222,7 +1222,7 @@ struct FlattenPass : public Pass {
RTLIL::Module *top_mod = NULL; RTLIL::Module *top_mod = NULL;
if (design->full_selection()) if (design->full_selection())
for (auto mod : design->modules()) for (auto mod : design->modules())
if (mod->get_bool_attribute("\\top")) if (mod->get_bool_attribute(ID(top)))
top_mod = mod; top_mod = mod;
std::set<RTLIL::Cell*> handled_cells; std::set<RTLIL::Cell*> handled_cells;

46
passes/techmap/tribuf.cc
View File

@ -63,38 +63,38 @@ struct TribufWorker {
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "$tribuf") if (cell->type == ID($tribuf))
tribuf_cells[sigmap(cell->getPort("\\Y"))].push_back(cell); tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
if (cell->type == "$_TBUF_") if (cell->type == ID($_TBUF_))
tribuf_cells[sigmap(cell->getPort("\\Y"))].push_back(cell); tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
if (cell->type.in("$mux", "$_MUX_")) if (cell->type.in(ID($mux), ID($_MUX_)))
{ {
IdString en_port = cell->type == "$mux" ? "\\EN" : "\\E"; IdString en_port = cell->type == ID($mux) ? ID(EN) : ID(E);
IdString tri_type = cell->type == "$mux" ? "$tribuf" : "$_TBUF_"; IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
if (is_all_z(cell->getPort("\\A")) && is_all_z(cell->getPort("\\B"))) { if (is_all_z(cell->getPort(ID(A))) && is_all_z(cell->getPort(ID(B)))) {
module->remove(cell); module->remove(cell);
continue; continue;
} }
if (is_all_z(cell->getPort("\\A"))) { if (is_all_z(cell->getPort(ID(A)))) {
cell->setPort("\\A", cell->getPort("\\B")); cell->setPort(ID(A), cell->getPort(ID(B)));
cell->setPort(en_port, cell->getPort("\\S")); cell->setPort(en_port, cell->getPort(ID(S)));
cell->unsetPort("\\B"); cell->unsetPort(ID(B));
cell->unsetPort("\\S"); cell->unsetPort(ID(S));
cell->type = tri_type; cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort("\\Y"))].push_back(cell); tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
continue; continue;
} }
if (is_all_z(cell->getPort("\\B"))) { if (is_all_z(cell->getPort(ID(B)))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort("\\S"))); cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID(S))));
cell->unsetPort("\\B"); cell->unsetPort(ID(B));
cell->unsetPort("\\S"); cell->unsetPort(ID(S));
cell->type = tri_type; cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort("\\Y"))].push_back(cell); tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
continue; continue;
} }
} }
@ -118,11 +118,11 @@ struct TribufWorker {
SigSpec pmux_b, pmux_s; SigSpec pmux_b, pmux_s;
for (auto cell : it.second) { for (auto cell : it.second) {
if (cell->type == "$tribuf") if (cell->type == ID($tribuf))
pmux_s.append(cell->getPort("\\EN")); pmux_s.append(cell->getPort(ID(EN)));
else else
pmux_s.append(cell->getPort("\\E")); pmux_s.append(cell->getPort(ID(E)));
pmux_b.append(cell->getPort("\\A")); pmux_b.append(cell->getPort(ID(A)));
module->remove(cell); module->remove(cell);
} }

30
passes/techmap/zinit.cc
View File

@ -62,12 +62,12 @@ struct ZinitPass : public Pass {
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
{ {
if (wire->attributes.count("\\init") == 0) if (wire->attributes.count(ID(init)) == 0)
continue; continue;
SigSpec wirebits = sigmap(wire); SigSpec wirebits = sigmap(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID(init));
wire->attributes.erase("\\init"); wire->attributes.erase(ID(init));
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
{ {
@ -90,12 +90,12 @@ struct ZinitPass : public Pass {
} }
pool<IdString> dff_types = { pool<IdString> dff_types = {
"$ff", "$dff", "$dffe", "$dffsr", "$adff", ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($adff),
"$_FF_", "$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_", ID($_FF_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
"$_DFFSR_NNN_", "$_DFFSR_NNP_", "$_DFFSR_NPN_", "$_DFFSR_NPP_", ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
"$_DFFSR_PNN_", "$_DFFSR_PNP_", "$_DFFSR_PPN_", "$_DFFSR_PPP_", ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
"$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_", ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_" ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)
}; };
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
@ -103,8 +103,8 @@ struct ZinitPass : public Pass {
if (!dff_types.count(cell->type)) if (!dff_types.count(cell->type))
continue; continue;
SigSpec sig_d = sigmap(cell->getPort("\\D")); SigSpec sig_d = sigmap(cell->getPort(ID(D)));
SigSpec sig_q = sigmap(cell->getPort("\\Q")); SigSpec sig_q = sigmap(cell->getPort(ID(Q)));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1) if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue; continue;
@ -120,14 +120,14 @@ struct ZinitPass : public Pass {
} }
Wire *initwire = module->addWire(NEW_ID, GetSize(initval)); Wire *initwire = module->addWire(NEW_ID, GetSize(initval));
initwire->attributes["\\init"] = initval; initwire->attributes[ID(init)] = initval;
for (int i = 0; i < GetSize(initwire); i++) for (int i = 0; i < GetSize(initwire); i++)
if (initval.bits.at(i) == State::S1) if (initval.bits.at(i) == State::S1)
{ {
sig_d[i] = module->NotGate(NEW_ID, sig_d[i]); sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]); module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
initwire->attributes["\\init"].bits.at(i) = State::S0; initwire->attributes[ID(init)].bits.at(i) = State::S0;
} }
else else
{ {
@ -137,8 +137,8 @@ struct ZinitPass : public Pass {
log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type), log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
log_signal(sig_q), log_signal(initval)); log_signal(sig_q), log_signal(initval));
cell->setPort("\\D", sig_d); cell->setPort(ID(D), sig_d);
cell->setPort("\\Q", initwire); cell->setPort(ID(Q), initwire);
} }
for (auto &it : initbits) for (auto &it : initbits)

4
passes/tests/test_cell.cc
View File

@ -43,7 +43,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
RTLIL::Wire *wire; RTLIL::Wire *wire;
if (cell_type == "$mux" || cell_type == "$pmux") if (cell_type.in("$mux", "$pmux"))
{ {
int width = 1 + xorshift32(8); int width = 1 + xorshift32(8);
int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8); int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort("\\Y", wire); cell->setPort("\\Y", wire);
} }
if (muxdiv && (cell_type == "$div" || cell_type == "$mod")) { if (muxdiv && cell_type.in("$div", "$mod")) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B")); auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B"));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y"))); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y")));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y")); module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y"));