mirror of https://github.com/YosysHQ/yosys.git
Remove extraneous synth_xilinx call
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@ -62,7 +62,6 @@ read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r
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hierarchy -top lutram_1w3r
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proc
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proc
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memory -nomap
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memory -nomap
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synth_xilinx
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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memory
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opt -full
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opt -full
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@ -83,7 +82,6 @@ read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r -chparam A_WIDTH 6
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hierarchy -top lutram_1w3r -chparam A_WIDTH 6
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proc
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proc
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memory -nomap
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memory -nomap
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synth_xilinx
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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memory
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opt -full
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opt -full
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