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ifndef __ICARUS__ -> ifdef YOSYS

This commit is contained in:
Eddie Hung 2020-01-01 17:33:47 -08:00
parent db04161eca
commit d0d3ab8f67
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/cells_sim.v
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@ -2160,13 +2160,13 @@ module DSP48E1 (
output reg [3:0] CARRYOUT, output reg [3:0] CARRYOUT,
output reg MULTSIGNOUT, output reg MULTSIGNOUT,
output OVERFLOW, output OVERFLOW,
`ifndef __ICARUS__ `ifdef YOSYS
(* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
`endif `endif
output reg signed [47:0] P, output reg signed [47:0] P,
output reg PATTERNBDETECT, output reg PATTERNBDETECT,
output reg PATTERNDETECT, output reg PATTERNDETECT,
`ifndef __ICARUS__ `ifdef YOSYS
(* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
`endif `endif
output [47:0] PCOUT, output [47:0] PCOUT,