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Add "hdlname" attribute 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-26 14:51:35 +01:00
parent c863796e9f
commit d0b9b1bece
2 changed files with 5 additions and 0 deletions
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3
README.md
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@ -315,6 +315,9 @@ Verilog Attributes and non-standard features
- The ``dynports'' attribute is used by the Verilog front-end to mark modules - The ``dynports'' attribute is used by the Verilog front-end to mark modules
that have ports with a width that depends on a parameter. that have ports with a width that depends on a parameter.
- The ``hdlname'' attribute is used by some passes to document the original
(HDL) name of a module when renaming a module.
- The ``keep`` attribute on cells and wires is used to mark objects that should - The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that never be removed by the optimizer. This is used for example for cells that
have hidden connections that are not part of the netlist, such as IO pads. have hidden connections that are not part of the netlist, such as IO pads.

2
passes/hierarchy/uniquify.cc
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@ -87,6 +87,8 @@ struct UniquifyPass : public Pass {
smod->name = newname; smod->name = newname;
cell->type = newname; cell->type = newname;
smod->set_bool_attribute("\\unique"); smod->set_bool_attribute("\\unique");
if (smod->attributes.count("\\hdlname") == 0)
smod->attributes["\\hdlname"] = string(log_id(tmod->name));
design->add(smod); design->add(smod);
did_something = true; did_something = true;