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More stringent check for flop cells

This commit is contained in:
Eddie Hung 2019-12-20 12:32:00 -08:00
parent 83d36394f8
commit d038cea3c7
1 changed files with 4 additions and 2 deletions
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6
passes/opt/opt_merge.cc
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@ -222,7 +222,8 @@ struct OptMergeWorker
return true; return true;
} }
if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) { if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") ||
cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) {
std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector(); std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector(); std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++) for (size_t i = 0; i < q1.size(); i++)
@ -324,7 +325,8 @@ struct OptMergeWorker
module->connect(RTLIL::SigSig(it.second, other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig); assign_map.add(it.second, other_sig);
if (cell->type.begins_with("$") && it.first == ID(Q)) { if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") ||
cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) {
for (auto c : it.second.chunks()) { for (auto c : it.second.chunks()) {
auto jt = c.wire->attributes.find(ID(init)); auto jt = c.wire->attributes.find(ID(init));
if (jt == c.wire->attributes.end()) if (jt == c.wire->attributes.end())