riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

rtlil: Dump empty connections when whole module is selected. 

Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
This commit is contained in:
Marcelina Kościelnicka 2021-12-11 16:53:54 +01:00
parent 21fbdb6638
commit d019b4e681
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
backends/rtlil/rtlil_backend.cc
View File

@ -358,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
bool first_conn_line = true; bool first_conn_line = true;
for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
bool show_conn = !only_selected; bool show_conn = !only_selected || design->selected_whole_module(module->name);
if (only_selected) { if (!show_conn) {
RTLIL::SigSpec sigs = it->first; RTLIL::SigSpec sigs = it->first;
sigs.append(it->second); sigs.append(it->second);
for (auto &c : sigs.chunks()) { for (auto &c : sigs.chunks()) {