mirror of https://github.com/YosysHQ/yosys.git
Added bram support
This commit is contained in:
Miodrag Milanovic
parent
6e210f26fa
commit
cf96f41c6d
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@ -1,7 +1,10 @@
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OBJS += techlibs/efinix/synth_efinix.o
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OBJS += techlibs/efinix/efinix_gbuf.o
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OBJS += techlibs/efinix/efinix_determine_init.o
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
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@ -0,0 +1,32 @@
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bram $__EFINIX_5K
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init 1
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abits 8 @a8d16
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dbits 16 @a8d16
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abits 9 @a9d8
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dbits 8 @a9d8
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abits 10 @a10d4
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dbits 4 @a10d4
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abits 11 @a11d2
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dbits 2 @a11d2
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abits 12 @a12d1
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dbits 1 @a12d1
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abits 8 @a8d20
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dbits 20 @a8d20
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abits 9 @a9d10
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dbits 10 @a9d10
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groups 2
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ports 1 1
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wrmode 1 0
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enable 1 1
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transp 0 2
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clocks 2 3
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clkpol 2 3
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endbram
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match $__EFINIX_5K
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min bits 256
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min efficiency 5
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shuffle_enable B
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endmatch
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@ -0,0 +1,65 @@
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module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 8;
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parameter CFG_DBITS = 20;
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parameter CFG_ENABLE_A = 2;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [5119:0] INIT = 5119'bx;
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parameter TRANSP2 = 0;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
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EFX_RAM_5K #(
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.READ_WIDTH(20),
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.WRITE_WIDTH(20),
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.OUTPUT_REG(1'b0),
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.RCLK_POLARITY(1'b1),
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.RE_POLARITY(1'b1),
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.WCLK_POLARITY(1'b1),
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.WE_POLARITY(1'b1),
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.WCLKE_POLARITY(1'b1),
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.WRITE_MODE(WRITEMODE_A),
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.INIT_0(INIT[ 0*256 +: 256]),
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.INIT_1(INIT[ 1*256 +: 256]),
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.INIT_2(INIT[ 2*256 +: 256]),
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.INIT_3(INIT[ 3*256 +: 256]),
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.INIT_4(INIT[ 4*256 +: 256]),
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.INIT_5(INIT[ 5*256 +: 256]),
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.INIT_6(INIT[ 6*256 +: 256]),
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.INIT_7(INIT[ 7*256 +: 256]),
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.INIT_8(INIT[ 8*256 +: 256]),
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.INIT_9(INIT[ 9*256 +: 256]),
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.INIT_A(INIT[10*256 +: 256]),
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.INIT_B(INIT[11*256 +: 256]),
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.INIT_C(INIT[12*256 +: 256]),
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.INIT_D(INIT[13*256 +: 256]),
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.INIT_E(INIT[14*256 +: 256]),
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.INIT_F(INIT[15*256 +: 256]),
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.INIT_10(INIT[16*256 +: 256]),
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.INIT_11(INIT[17*256 +: 256]),
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.INIT_12(INIT[18*256 +: 256]),
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.INIT_13(INIT[19*256 +: 256])
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) _TECHMAP_REPLACE_ (
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.WDATA(A1DATA),
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.WADDR(A1ADDR),
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.WE(A1EN),
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.WCLK(CLK2),
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.WCLKE(1'b1),
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.RDATA(B1DATA),
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.RADDR(B1ADDR),
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.RE(B1EN),
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.RCLK(CLK3)
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);
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endmodule
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@ -35,10 +35,73 @@ module EFX_FF(
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parameter D_POLARITY = 1;
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endmodule
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module EFX_GBUFCE (
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module EFX_GBUFCE(
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input CE,
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input I,
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output O
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);
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parameter CE_POLARITY = 1'b1;
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endmodule
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module EFX_RAM_5K(
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input [WRITE_WIDTH-1:0] WDATA,
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input [WRITE_ADDR_WIDTH-1:0] WADDR,
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input WE,
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input WCLK,
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input WCLKE,
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output [READ_WIDTH-1:0] RDATA,
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input [READ_ADDR_WIDTH-1:0] RADDR,
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input RE,
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input RCLK
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);
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parameter READ_WIDTH = 20;
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parameter WRITE_WIDTH = 20;
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parameter OUTPUT_REG = 1'b0;
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parameter RCLK_POLARITY = 1'b1;
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parameter RE_POLARITY = 1'b1;
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parameter WCLK_POLARITY = 1'b1;
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parameter WE_POLARITY = 1'b1;
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parameter WCLKE_POLARITY = 1'b1;
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parameter WRITE_MODE = "READ_FIRST";
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parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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localparam READ_ADDR_WIDTH =
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(READ_WIDTH == 16) ? 8 : // 256x16
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(READ_WIDTH == 8) ? 9 : // 512x8
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(READ_WIDTH == 4) ? 10 : // 1024x4
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(READ_WIDTH == 2) ? 11 : // 2048x2
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(READ_WIDTH == 1) ? 12 : // 4096x1
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(READ_WIDTH == 20) ? 8 : // 256x20
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(READ_WIDTH == 10) ? 9 : // 512x10
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(READ_WIDTH == 5) ? 10 : -1; // 1024x5
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localparam WRITE_ADDR_WIDTH =
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(WRITE_WIDTH == 16) ? 8 : // 256x16
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(WRITE_WIDTH == 8) ? 9 : // 512x8
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(WRITE_WIDTH == 4) ? 10 : // 1024x4
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(WRITE_WIDTH == 2) ? 11 : // 2048x2
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(WRITE_WIDTH == 1) ? 12 : // 4096x1
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(WRITE_WIDTH == 20) ? 8 : // 256x20
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(WRITE_WIDTH == 10) ? 9 : // 512x10
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(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
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endmodule
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@ -0,0 +1,89 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EfinixDetermineInitPass : public Pass {
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EfinixDetermineInitPass() : Pass("efinix_determine_init", "Efinix: Determine the init value of cells") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" efinix_determine_init [selection]\n");
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log("\n");
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log("Determine the init value of cells that doesn't allow unknown init value.\n");
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log("\n");
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}
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Const determine_init(Const init)
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{
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for (int i = 0; i < GetSize(init); i++) {
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if (init[i] != State::S0 && init[i] != State::S1)
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init[i] = State::S0;
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}
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return init;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing EFINIX_DETERMINE_INIT pass (determine init value for cells).\n");
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extra_args(args, args.size(), design);
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int cnt = 0;
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\EFX_RAM_5K")
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{
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cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));
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cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
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cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
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cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
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cell->setParam("\\INIT_4", determine_init(cell->getParam("\\INIT_4")));
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cell->setParam("\\INIT_5", determine_init(cell->getParam("\\INIT_5")));
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cell->setParam("\\INIT_6", determine_init(cell->getParam("\\INIT_6")));
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cell->setParam("\\INIT_7", determine_init(cell->getParam("\\INIT_7")));
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cell->setParam("\\INIT_8", determine_init(cell->getParam("\\INIT_8")));
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cell->setParam("\\INIT_9", determine_init(cell->getParam("\\INIT_9")));
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cell->setParam("\\INIT_A", determine_init(cell->getParam("\\INIT_A")));
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cell->setParam("\\INIT_B", determine_init(cell->getParam("\\INIT_B")));
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cell->setParam("\\INIT_C", determine_init(cell->getParam("\\INIT_C")));
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cell->setParam("\\INIT_D", determine_init(cell->getParam("\\INIT_D")));
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cell->setParam("\\INIT_E", determine_init(cell->getParam("\\INIT_E")));
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cell->setParam("\\INIT_F", determine_init(cell->getParam("\\INIT_F")));
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cell->setParam("\\INIT_10", determine_init(cell->getParam("\\INIT_10")));
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cell->setParam("\\INIT_11", determine_init(cell->getParam("\\INIT_11")));
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cell->setParam("\\INIT_12", determine_init(cell->getParam("\\INIT_12")));
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cell->setParam("\\INIT_13", determine_init(cell->getParam("\\INIT_13")));
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cnt++;
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}
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}
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}
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log_header(design, "Updated %d cells with determined init value.\n", cnt);
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}
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} EfinixDetermineInitPass;
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PRIVATE_NAMESPACE_END
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@ -150,6 +150,13 @@ struct SynthEfinixPass : public ScriptPass
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run("synth -run coarse");
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}
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if (check_label("map_bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/efinix/bram.txt");
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run("techmap -map +/efinix/brams_map.v");
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run("efinix_determine_init");
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}
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if (check_label("fine"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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