mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2133 from dh73/nodev_head
Adding latch tests for shift&mask AST dynamic part-select enhancements
This commit is contained in:
commit
cf67e6a397
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@ -104,3 +104,59 @@ design -copy-from gate -as gate gate
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miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
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sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
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### Latches
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## Issue 1990
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design -reset
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read_verilog ./dynamic_part_select/latch_1990.v
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hierarchy -top latch_1990; prep; async2sync
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rename -top gold
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design -stash gold
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read_verilog ./dynamic_part_select/latch_1990_gate.v
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hierarchy -top latch_1990_gate; prep
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rename -top gate
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design -stash gate
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design -copy-from gold -as gold gold
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design -copy-from gate -as gate gate
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miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
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sat -prove-asserts -show-public -verify -set-init-zero equiv
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###
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## Part select with obvious latch, expected to fail due comparison with old shift&mask AST transformation
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design -reset
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read_verilog ./dynamic_part_select/latch_002.v
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hierarchy -top latch_002; prep; async2sync
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rename -top gold
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design -stash gold
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read_verilog ./dynamic_part_select/latch_002_gate.v
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hierarchy -top latch_002_gate; prep; async2sync
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rename -top gate
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design -stash gate
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design -copy-from gold -as gold gold
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design -copy-from gate -as gate gate
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miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
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sat -prove-asserts -seq 10 -show-public -falsify -set-init-zero equiv
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## Part select + latch, with no shift&mask
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design -reset
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read_verilog ./dynamic_part_select/latch_002.v
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hierarchy -top latch_002; prep; async2sync
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rename -top gold
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design -stash gold
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read_verilog ./dynamic_part_select/latch_002_gate_good.v
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hierarchy -top latch_002_gate; prep; async2sync
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rename -top gate
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design -stash gate
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design -copy-from gold -as gold gold
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design -copy-from gate -as gate gate
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miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
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sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
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@ -1,8 +1,9 @@
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`default_nettype none
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module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input en,
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire en,
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output reg [WIDTH-1:0] dout);
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reg [SELW:0] sel;
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@ -16,4 +17,3 @@ module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2*
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end
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end
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endmodule
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@ -1,8 +1,9 @@
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`default_nettype none
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module forloop_select_gate (clk, ctrl, din, en, dout);
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input clk;
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input [3:0] ctrl;
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input [15:0] din;
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input en;
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input wire clk;
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input wire [3:0] ctrl;
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input wire [15:0] din;
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input wire en;
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output reg [15:0] dout;
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reg [4:0] sel;
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always @(posedge clk)
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@ -0,0 +1,13 @@
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`default_nettype none
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module latch_002
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(dword, sel, st, vect);
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output reg [63:0] dword;
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input wire [7:0] vect;
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input wire [7:0] sel;
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input wire st;
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always @(*) begin
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if (st)
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dword[8*sel +:8] <= vect[7:0];
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end
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endmodule // latch_002
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@ -0,0 +1,18 @@
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`default_nettype none
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module latch_002_gate(dword, vect, sel, st);
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output reg [63:0] dword;
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input wire [7:0] vect;
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input wire [7:0] sel;
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input wire st;
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reg [63:0] mask;
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reg [63:0] data;
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always @*
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case (|(st))
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1'b 1:
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begin
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mask = (8'b 11111111)<<((((8)*(sel)))+(0));
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data = ((8'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0));
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dword <= ((dword)&(~(mask)))|(data);
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end
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endcase
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endmodule
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@ -0,0 +1,141 @@
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`default_nettype none
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module latch_002_gate (dword, vect, sel, st);
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output reg [63:0] dword;
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input wire [7:0] vect;
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input wire [7:0] sel;
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input st;
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always @*
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case (|(st))
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1'b 1:
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case ((((8)*(sel)))+(0))
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0:
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dword[7:0] <= vect[7:0];
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1:
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dword[8:1] <= vect[7:0];
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2:
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dword[9:2] <= vect[7:0];
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3:
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dword[10:3] <= vect[7:0];
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4:
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dword[11:4] <= vect[7:0];
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5:
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dword[12:5] <= vect[7:0];
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6:
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dword[13:6] <= vect[7:0];
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7:
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dword[14:7] <= vect[7:0];
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8:
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dword[15:8] <= vect[7:0];
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9:
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dword[16:9] <= vect[7:0];
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10:
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dword[17:10] <= vect[7:0];
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11:
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dword[18:11] <= vect[7:0];
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12:
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dword[19:12] <= vect[7:0];
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13:
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dword[20:13] <= vect[7:0];
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14:
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dword[21:14] <= vect[7:0];
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15:
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dword[22:15] <= vect[7:0];
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16:
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dword[23:16] <= vect[7:0];
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17:
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dword[24:17] <= vect[7:0];
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18:
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dword[25:18] <= vect[7:0];
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19:
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dword[26:19] <= vect[7:0];
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20:
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dword[27:20] <= vect[7:0];
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21:
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dword[28:21] <= vect[7:0];
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22:
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dword[29:22] <= vect[7:0];
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23:
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dword[30:23] <= vect[7:0];
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24:
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dword[31:24] <= vect[7:0];
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25:
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dword[32:25] <= vect[7:0];
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26:
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dword[33:26] <= vect[7:0];
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27:
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dword[34:27] <= vect[7:0];
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28:
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dword[35:28] <= vect[7:0];
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29:
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dword[36:29] <= vect[7:0];
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30:
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dword[37:30] <= vect[7:0];
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31:
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dword[38:31] <= vect[7:0];
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32:
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dword[39:32] <= vect[7:0];
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33:
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dword[40:33] <= vect[7:0];
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34:
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dword[41:34] <= vect[7:0];
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35:
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dword[42:35] <= vect[7:0];
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36:
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dword[43:36] <= vect[7:0];
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37:
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dword[44:37] <= vect[7:0];
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38:
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dword[45:38] <= vect[7:0];
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39:
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dword[46:39] <= vect[7:0];
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40:
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dword[47:40] <= vect[7:0];
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41:
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dword[48:41] <= vect[7:0];
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42:
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dword[49:42] <= vect[7:0];
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43:
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dword[50:43] <= vect[7:0];
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44:
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dword[51:44] <= vect[7:0];
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45:
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dword[52:45] <= vect[7:0];
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46:
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dword[53:46] <= vect[7:0];
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47:
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dword[54:47] <= vect[7:0];
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48:
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dword[55:48] <= vect[7:0];
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49:
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dword[56:49] <= vect[7:0];
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50:
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dword[57:50] <= vect[7:0];
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51:
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dword[58:51] <= vect[7:0];
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52:
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dword[59:52] <= vect[7:0];
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53:
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dword[60:53] <= vect[7:0];
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54:
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dword[61:54] <= vect[7:0];
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55:
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dword[62:55] <= vect[7:0];
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56:
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dword[63:56] <= vect[7:0];
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57:
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dword[63:57] <= vect[7:0];
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58:
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dword[63:58] <= vect[7:0];
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59:
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dword[63:59] <= vect[7:0];
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60:
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dword[63:60] <= vect[7:0];
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61:
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dword[63:61] <= vect[7:0];
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62:
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dword[63:62] <= vect[7:0];
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63:
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dword[63:63] <= vect[7:0];
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endcase
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endcase
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endmodule
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@ -0,0 +1,12 @@
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module latch_1990 #(
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parameter BUG = 1
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) (
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(* nowrshmsk = !BUG *)
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output reg [1:0] x
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);
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wire z = 0;
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integer i;
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always @*
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for (i = 0; i < 2; i=i+1)
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x[z^i] = z^i;
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endmodule
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@ -0,0 +1,6 @@
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`default_nettype none
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module latch_1990_gate
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(output wire [1:0] x);
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assign x = 2'b10;
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endmodule // latch_1990_gate
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@ -1,8 +1,9 @@
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`default_nettype none
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module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input [SELW-1:0] sel,
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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@ -1,8 +1,9 @@
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`default_nettype none
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module multiple_blocking_gate (clk, ctrl, din, sel, dout);
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input clk;
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input [4:0] ctrl;
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input [1:0] din;
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input [0:0] sel;
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input wire clk;
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input wire [4:0] ctrl;
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input wire [1:0] din;
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input wire [0:0] sel;
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output reg [31:0] dout;
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reg [5:0] a;
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reg [0:0] b;
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@ -1,8 +1,9 @@
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`default_nettype none
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module nonblocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input [SELW-1:0] sel,
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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@ -1,8 +1,9 @@
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`default_nettype none
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module nonblocking_gate (clk, ctrl, din, sel, dout);
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input clk;
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input [4:0] ctrl;
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input [1:0] din;
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input [0:0] sel;
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input wire clk;
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input wire [4:0] ctrl;
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input wire [1:0] din;
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input wire [0:0] sel;
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output reg [31:0] dout;
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always @(posedge clk)
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begin
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@ -1,8 +1,9 @@
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`default_nettype none
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module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input [SELW-1:0] sel,
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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always @(posedge clk)
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@ -1,8 +1,9 @@
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`default_nettype none
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module original_gate (clk, ctrl, din, sel, dout);
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input clk;
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input [4:0] ctrl;
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input [1:0] din;
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input [0:0] sel;
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input wire clk;
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input wire [4:0] ctrl;
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input wire [1:0] din;
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input wire [0:0] sel;
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output reg [31:0] dout;
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always @(posedge clk)
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case (({(ctrl)*(sel)})+(0))
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@ -1,8 +1,10 @@
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`default_nettype none
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module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input [SELW-1:0] sel,
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(input wire clk,
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input wire reset,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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reg [SELW:0] i;
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@ -16,8 +18,6 @@ module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SE
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dout[i*rval+:SLICE] <= 32'hDEAD;
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end
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end
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//else begin
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dout[ctrl*sel+:SLICE] <= din;
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//end
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end
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endmodule
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@ -1,8 +1,10 @@
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module reset_test_gate (clk, ctrl, din, sel, dout);
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input clk;
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input [4:0] ctrl;
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input [1:0] din;
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input [0:0] sel;
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`default_nettype none
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module reset_test_gate (clk, reset, ctrl, din, sel, dout);
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input wire clk;
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input wire reset;
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input wire [4:0] ctrl;
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input wire [1:0] din;
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input wire [0:0] sel;
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output reg [31:0] dout;
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reg [1:0] i;
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wire [0:0] rval;
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@ -1,8 +1,9 @@
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`default_nettype none
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module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input [SELW-1:0] sel,
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire [SELW-1:0] sel,
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output reg [WIDTH-1:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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@ -1,8 +1,9 @@
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`default_nettype none
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module reversed_gate (clk, ctrl, din, sel, dout);
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input clk;
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input [4:0] ctrl;
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input [15:0] din;
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input [3:0] sel;
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input wire clk;
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input wire [4:0] ctrl;
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input wire [15:0] din;
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input wire [3:0] sel;
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output reg [31:0] dout;
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always @(posedge clk)
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case ((({(32)-((ctrl)*(sel))})+(1))-(2))
|
||||
|
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