riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

write_xaiger: cleanup

This commit is contained in:
Eddie Hung 2020-01-09 14:03:43 -08:00
parent 73d89b3964
commit ceabd5bc39
1 changed files with 15 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
backends/aiger/xaiger.cc
View File

@ -243,23 +243,21 @@ struct XAigerWriter
if (port_wire->port_output) { if (port_wire->port_output) {
arrivals.clear(); arrivals.clear();
auto it = port_wire->attributes.find("\\abc9_arrival"); auto it = port_wire->attributes.find("\\abc9_arrival");
if (it != port_wire->attributes.end()) { if (it == port_wire->attributes.end())
if (it->second.flags == 0) continue;
arrivals.emplace_back(it->second.as_int()); if (it->second.flags == 0)
else arrivals.emplace_back(it->second.as_int());
for (const auto &tok : split_tokens(it->second.decode_string())) else
arrivals.push_back(atoi(tok.c_str())); for (const auto &tok : split_tokens(it->second.decode_string()))
} arrivals.push_back(atoi(tok.c_str()));
if (!arrivals.empty()) { if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); auto jt = arrivals.begin();
auto jt = arrivals.begin(); for (auto bit : sigmap(conn.second)) {
for (auto bit : sigmap(conn.second)) { arrival_times[bit] = *jt;
arrival_times[bit] = *jt; if (arrivals.size() > 1)
if (arrivals.size() > 1) jt++;
jt++;
}
} }
} }
} }