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Move the last presentation slides

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Krystine Sherwin 2023-08-08 09:50:36 +12:00
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62
docs/source/using_yosys/more_scripting/selections.rst
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@ -199,15 +199,22 @@ tools).
of the circuit.
- :doc:`/cmd/show`.
- :doc:`/cmd/dump`.
- :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a
design dynamically.
Reorganizing a module
^^^^^^^^^^^^^^^^^^^^^
Changing design hierarchy
^^^^^^^^^^^^^^^^^^^^^^^^^
Commands such as ``flatten`` and ``submod`` can be used to change the design
hierarchy, i.e. flatten the hierarchy or moving parts of a module to a
submodule. This has applications in synthesis scripts as well as in reverse
engineering and analysis. An example using ``submod`` is shown below for
reorganizing a module in Yosys and checking the resulting circuit.
.. literalinclude:: ../../../resources/PRESENTATION_ExOth/scrambler.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExOth/scrambler.v``
.. code:: yoscrypt
read_verilog scrambler.v
@ -225,15 +232,10 @@ Reorganizing a module
.. figure:: ../../../images/res/PRESENTATION_ExOth/scrambler_p02.*
:class: width-helper
Analysis of circuit behavior
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Analyzing the resulting circuit with :doc:`/cmd/eval`:
.. code:: text
> read_verilog scrambler.v
> hierarchy; proc;; cd scrambler
> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
> cd xorshift32
> rename n2 in
> rename n1 out
@ -249,3 +251,45 @@ Analysis of circuit behavior
-------------------- ---------- ---------- -------------------------------------
\in 745495504 2c6f5bd0 00101100011011110101101111010000
\out 632435482 25b2331a 00100101101100100011001100011010
Behavioral changes
^^^^^^^^^^^^^^^^^^
Commands such as ``techmap`` can be used to make behavioral changes to the
design, for example changing asynchronous resets to synchronous resets. This has
applications in design space exploration (evaluation of various architectures
for one circuit).
The following techmap map file replaces all positive-edge async reset flip-flops
with positive-edge sync reset flip-flops. The code is taken from the example
Yosys script for ASIC synthesis of the Amber ARMv2 CPU.
.. code:: verilog
(* techmap_celltype = "$adff" *)
module adff2dff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire [1023:0] _TECHMAP_DO_ = "proc";
wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
always @(posedge CLK)
if (ARST)
Q <= ARST_VALUE;
else
<= D;
endmodule
For more on the ``techmap`` command, see the page on
:doc:`/yosys_internals/techmap` or the
:doc:`techmap command reference document</cmd/techmap>`.

12
manual/.gitignore vendored
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@ -1,12 +0,0 @@
*.aux
*.bbl
*.blg
*.idx
*.log
*.out
*.pdf
*.toc
*.snm
*.nav
*.vrb
*.ok

112
manual/PRESENTATION_ExAdv.tex
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@ -1,112 +0,0 @@
\section{Yosys by example -- Advanced Synthesis}
\begin{frame}
\sectionpage
\end{frame}
\begin{frame}{Overview}
This section contains 4 subsections:
\begin{itemize}
\item Using selections
\item Advanced uses of techmap
\item Coarse-grain synthesis
\item Automatic design changes
\end{itemize}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Automatic design changes}
\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}
\subsubsection{Changing the design from Yosys}
\begin{frame}{\subsubsecname}
Yosys commands can be used to change the design in memory. Examples of this are:
\begin{itemize}
\item {\bf Changes in design hierarchy} \\
Commands such as {\tt flatten} and {\tt submod} can be used to change the design hierarchy, i.e.
flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis
scripts as well as in reverse engineering and analysis.
\item {\bf Behavioral changes} \\
Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
changing asynchronous resets to synchronous resets. This has applications in design space exploration
(evaluation of various architectures for one circuit).
\end{itemize}
\end{frame}
\subsubsection{Example: Async reset to sync reset}
\begin{frame}[t, fragile]{\subsubsecname}
The following techmap map file replaces all positive-edge async reset flip-flops with
positive-edge sync reset flip-flops. The code is taken from the example Yosys script
for ASIC synthesis of the Amber ARMv2 CPU.
\begin{columns}
\column[t]{6cm}
\vbox to 0cm{
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
(* techmap_celltype = "$adff" *)
module adff2dff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire [1023:0] _TECHMAP_DO_ = "proc";
wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
\end{lstlisting}
\vss}
\column[t]{4cm}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
// ..continued..
always @(posedge CLK)
if (ARST)
Q <= ARST_VALUE;
else
<= D;
endmodule
\end{lstlisting}
\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Summary}
\begin{frame}{\subsecname}
\begin{itemize}
\item A lot can be achieved in Yosys just with the standard set of commands.
\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
\end{itemize}
\bigskip
\bigskip
\begin{center}
Questions?
\end{center}
\bigskip
\bigskip
\begin{center}
\url{https://yosyshq.net/yosys/}
\end{center}
\end{frame}

2
manual/clean.sh
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@ -1,2 +0,0 @@
#!/bin/bash
for f in $( find . -name .gitignore ); do sed -Ee "s,^,find ${f%.gitignore} -name ',; s,$,' | xargs rm -f,;" $f; done | bash -v

54
manual/presentation.sh
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@ -1,54 +0,0 @@
#!/bin/bash
fast_mode=false
set -- $(getopt fu "$@")
while [ $# -gt 0 ]; do
case "$1" in
-f)
fast_mode=true
;;
--)
shift
break
;;
-*)
echo "$0: error - unrecognized option $1" 1>&2
exit 1
;;
*)
break
esac
shift
done
PDFTEX_OPT="-shell-escape -halt-on-error"
set -ex
if ! $fast_mode; then
! md5sum *.aux *.snm *.nav *.toc > autoloop.old
make -C PRESENTATION_Intro
make -C PRESENTATION_ExSyn
make -C PRESENTATION_ExAdv
make -C PRESENTATION_ExOth
make -C PRESENTATION_Prog
fi
set -ex
pdflatex $PDFTEX_OPT presentation.tex
if ! $fast_mode; then
while
md5sum *.aux *.snm *.nav *.toc > autoloop.new
! cmp autoloop.old autoloop.new
do
cp autoloop.new autoloop.old
pdflatex $PDFTEX_OPT presentation.tex
done
rm -f autoloop.old
rm -f autoloop.new
fi

162
manual/presentation.tex
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@ -1,162 +0,0 @@
\documentclass{beamer}
\hypersetup{bookmarksdepth=5}
\usepackage[T1]{fontenc} % required for luximono!
\usepackage{lmodern}
\usepackage[scaled=0.8]{luximono} % typewriter font with bold face
% To install the luximono font files:
% getnonfreefonts-sys --all or
% getnonfreefonts-sys luximono
%
% when there are trouble you might need to:
% - Create /etc/texmf/updmap.d/99local-luximono.cfg
% containing the single line: Map ul9.map
% - Run update-updmap followed by mktexlsr and updmap-sys
%
% This commands must be executed as root with a root environment
% (i.e. run "sudo su" and then execute the commands in the root
% shell, don't just prefix the commands with "sudo").
% formats the text according the set language
\usepackage[english]{babel}
\usepackage{amsmath}
\usepackage{multirow}
\usepackage{booktabs}
\usepackage{listings}
\usepackage{setspace}
\usepackage{skull}
\usepackage{units}
\usepackage{tikz}
\usetikzlibrary{calc}
\usetikzlibrary{arrows}
\usetikzlibrary{scopes}
\usetikzlibrary{through}
\usetikzlibrary{shapes.geometric}
\lstset{basicstyle=\ttfamily}
\def\B#1{{\tt\textbackslash{}#1}}
\def\C#1{\lstinline[language=C++]{#1}}
\def\V#1{\lstinline[language=Verilog]{#1}}
\lstdefinelanguage{liberty}{
morecomment=[s]{/*}{*/},
morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff},
morestring=[b]",
}
\lstdefinelanguage{rtlil}{
morecomment=[l]{\#},
morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end},
morestring=[b]",
}
\lstdefinelanguage{ys}{
morecomment=[l]{\#},
}
\lstset{
commentstyle=\color{YosysGreen},
}
\newenvironment{boxalertenv}{\begin{altenv}%
{\usebeamertemplate{alerted text begin}\usebeamercolor[fg]{alerted text}\usebeamerfont{alerted text}\setlength{\fboxsep}{1pt}\colorbox{bg}}
{\usebeamertemplate{alerted text end}}{\color{.}}{}}{\end{altenv}}
\newcommand<>{\boxalert}[1]{{%
\begin{boxalertenv}#2{#1}\end{boxalertenv}%
}}
\newcommand{\subsectionpagesuffix}{
\vfill\begin{centering}
{\usebeamerfont{subsection name}\usebeamercolor[fg]{subsection name}of \sectionname~\insertsectionnumber}
\vskip1em\par
\setbeamercolor{graybox}{bg=gray}
\begin{beamercolorbox}[sep=8pt,center]{graybox}
\usebeamerfont{subsection title}\insertsection\par
\end{beamercolorbox}
\end{centering}}
\title{Yosys Open SYnthesis Suite}
\author{Claire Xenia Wolf}
\institute{https://yosyshq.net/yosys/}
\usetheme{Madrid}
\usecolortheme{seagull}
\beamertemplatenavigationsymbolsempty
\definecolor{YosysGreen}{RGB}{85,136,102}
\definecolor{MyBlue}{RGB}{85,130,180}
\setbeamercolor{title}{fg=black,bg=YosysGreen!70}
\setbeamercolor{titlelike}{fg=black,bg=YosysGreen!70}
\setbeamercolor{frametitle}{fg=black,bg=YosysGreen!70}
\setbeamercolor{block title}{fg=black,bg=YosysGreen!70}
\setbeamercolor{item projected}{fg=black,bg=YosysGreen}
\begin{document}
\begin{frame}
\titlepage
\end{frame}
\setcounter{section}{-3}
\section{Abstract}
\begin{frame}{Abstract}
Yosys is the first full-featured open source software for Verilog HDL
synthesis. It supports most of Verilog-2005 and is well tested with
real-world designs from the ASIC and FPGA world.
\bigskip
Learn how to use Yosys to create your own custom synthesis flows and
discover why open source HDL synthesis is important for researchers,
hobbyists, educators and engineers alike.
\bigskip
This presentation covers basic concepts of Yosys, writing synthesis scripts
for a wide range of applications, creating Yosys scripts for various
non-synthesis applications (such as formal equivalence checking) and
writing extensions to Yosys using the C++ API.
\end{frame}
\section{About me}
\begin{frame}{About me}
Hi! I'm Claire Xenia Wolf.
\bigskip
I like writing open source software. For example:
\begin{itemize}
\item Yosys
\item OpenSCAD (now maintained by Marius Kintel)
\item SPL (a not very popular scripting language)
\item EmbedVM (a very simple compiler+vm for 8 bit micros)
\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG)
\item ROCK Linux (discontinued since 2010)
\end{itemize}
\end{frame}
\section{Outline}
\begin{frame}{Outline}
Yosys is an Open Source Verilog synthesis tool, and more.
\bigskip
Outline of this presentation:
\begin{itemize}
\item Introduction to the field and Yosys
\item Yosys by example: synthesis
\item Yosys by example: advanced synthesis
\item Yosys by example: beyond synthesis
\item Writing Yosys extensions in C++
\end{itemize}
\end{frame}
\include{PRESENTATION_Intro}
\include{PRESENTATION_ExSyn}
\include{PRESENTATION_ExAdv}
\include{PRESENTATION_ExOth}
\include{PRESENTATION_Prog}
\end{document}